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3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 1 general description the 3885 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3885 group is designed for keyboard controller for the note book pc. the multi-master i 2 c-bus interface can be added by option. features basic machine-language instructions ...................................... 71 minimum instruction execution time .................................. 0.5 s (at 8 mhz oscillation frequency) memory size rom ................................................................. 32k to 60k bytes ram ............................................................... 1024 to 2048 bytes programmable input/output ports ............................................ 72 software pull-up transistors ....................................................... 8 interrupts ................................................. 22 sources, 16 vectors timers ............................................................................. 8-bit ? 4 watchdog timer ............................................................ 16-bit ? 1 pwm output .................................................................. 14-bit ? 2 serial i/o ....................... 8-bit ? 1(uart or clock-synchronized) multi-master i 2 c bus interface (option) ........................ 1 channel lpc interface .............................................................. 2 channels serialized irq .................................................................. 3 factor a-d converter ............................................... 10-bit ? 8 channels d-a converter ................................................. 8-bit ? 2 channels comparator circuit ...................................................... 8 channels clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage ................................................ 3.0 to 3.6 v power dissipation in high-speed mode .......................................................... 20 mw (at 8 mhz oscillation frequency, at 3.3 v power source voltage) in low-speed mode ......................................................... 330 mw (at 32 khz oscillation frequency, at 3.3 v power source voltage) operating temperature range .................................... ?0 to 85? supply voltage ................................................. v cc = 3.3 ?0.3v program/erase voltage ................................. v pp = 5.0 v ?10 % programming method ...................... programming in unit of byte erasing method parallel i/o mode cpu reprogramming mode program/erase control by software command number of times for programming/erasing ............................ 100 operating temperature range (at programming/erasing) ........................................................................ room temperature application note book pc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 /pwm 00 p3 1 /pwm 10 p6 2 /an 2 p6 1 /an 1 p4 4 /r x d p4 3 /int 1 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 av ss p6 7 /an 7 v ref v cc p8 0 /lad 0 p8 1 /lad 1 p8 2 /lad 2 p8 3 /lad 3 p8 4 /lframe p8 5 /lreset p8 6 /lclk p8 7 /serirq p4 2 /int 0 cnv ss x in x out v ss reset p4 0 /x cout p4 1 /x cin p1 6 p1 7 p2 6 (led 2 ) p2 5 (led 1 ) p2 4 (led 0 ) p2 3 p2 2 p2 1 p2 0 /cmp ref p3 4 p3 5 p0 0 p0 4 p0 5 p0 6 p0 7 p1 1 p1 2 p1 3 p1 4 p1 5 p1 0 p0 1 p0 2 p3 2 p3 3 p3 6 p3 7 p0 3 p2 7 (led 3 ) p6 0 /an 0 p7 7 /s cl p7 6 /s da p7 5 /int 41 p7 4 /int 31 p7 2 p7 1 p7 0 p5 7 /da 2 /pwm 11 p5 0 /int 5 p4 5 /t x d p7 3 /int 21 p5 5 /cntr 1 p5 4 /cntr 0 p5 6 /da 1 /pwm 01 p4 7 /s rdy /clkrun p5 2 /int 30 p5 3 /int 40 p5 1 /int 20 p4 6 /s clk 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 m38857m8-xxxhp m38858mc-xxxhp M38859M8-XXXHP m38859ffhp v pp : flash memory version fig. 1 pin configuration package type : 80p6q-a pin configuration (top view)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 2 functional block diagram (package : 80p6q-a) fig. 2 functional block diagram i n t 0 , c n t r 0 c n t r 1 v r e f a v s s r a m r o m c p u a x y s p c h p c l p s v s s 3 0 r e s e t 2 5 v c c 7 1 2 4 c n v s s p 5 ( 8 ) p 7 ( 8 ) 2 4 6 8 3 5 7 9 p 8 ( 8 ) p 6 ( 8 ) 7 4 7 6 7 8 8 0 7 5 7 7 7 9 1 7 2 7 3 x i n 2 8 2 9 s i / o ( 8 ) d - a c o n v e r t e r 2 ( 8 ) r e s e t i n p u t c l o c k g e n e r a t i n g c i r c u i t m a i n - c l o c k i n p u t m a i n - c l o c k o u t p u t a - d c o n v e r t e r ( 1 0 ) t i m e r y ( 8 ) t i m e r x ( 8 ) p r e s c a l e r 1 2 ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) i / o p o r t p 5 i / o p o r t p 7 i / o p o r t p 8 i / o p o r t p 6 s u b - c l o c k i n p u t x o u t x c i n x c o u t s u b - c l o c k o u t p u t w a t c h d o g t i m e r r e s e t p 0 ( 8 ) p 1 ( 8 ) p 2 ( 8 ) p 3 ( 8 ) i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 i / o p o r t p 3 k e y - o n w a k e - u p x c i n x c o u t p 4 ( 8 ) i / o p o r t p 4 c o m p a r a t o r i n t 1 p w m 0 ( 1 4 ) p w m 1 ( 1 4 ) p w m 0 0 , p w m 0 1 p w m 1 0 , p w m 1 1 l p c i n t e r f a c e i c 2 s c l s d a i n t 4 1 i n t 2 1 , i n t 3 1 , 6 3 6 5 6 7 6 9 6 4 6 6 6 8 7 0 d - a c o n v e r t e r 1 ( 8 ) 1 0 1 2 1 4 1 6 1 1 1 3 1 5 1 7 1 8 2 0 2 2 2 6 1 9 2 1 2 3 2 7 5 5 5 7 5 9 6 1 5 6 5 8 6 0 6 2 3 1 3 3 3 5 3 7 3 2 3 4 3 6 3 8 3 9 4 1 4 3 4 5 4 0 4 2 4 4 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 i n t 4 0 , i n t 2 0 , i n t 3 0 , i n t 5 c l k r u n c m p r e f
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3 v cc , v ss pin description functions name pin apply voltage of 3.0 v 10 % to vcc, and 0 v to vss. connected to v ss . in the flash memory version, this pin functions as the v pp power source input pin. reference voltage input pin for a-d and d-a converters. analog power source input pin for a-d and d-a converters. connect to v ss . reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. p2 4 to p2 7 (4 bits) are enabled to output large current for led drive. 8-bit i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. these pins function as key-on wake-up and compara- tor input. these pins are enabled to control pull-up. power source table 1 pin description (1) function except a port function comparator reference power source input pin reference voltage analog power source clock input clock output i/o port p0 i/o port p1 v ref av ss cnv ss input reset reset input x in x out p0 0 p0 7 p1 0 p1 7 p2 1 p2 7 key-on wake-up input pins comparator input pins pwm output pins key-on wake-up input pins comparator input pins i/o port p2 i/o port p3 p3 0 /pwm 00 p3 1 /pwm 10 p3 2 p3 7 cnv ss p2 0 /cmp ref
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 4 functions name pin p4 0 /x cout p4 1 /x cin 8-bit i/o port with the same function as port p0 cmos compatible input level p4 0 , p4 1 : cmos 3-state output structure p4 2 -p4 7 : cmos 3-state output structure or n- channel open-drain output structure each pin level of p4 2 to p4 6 can be read even in output port mode. function except a port function table 2 pin description (2) sub-clock generating circuit i/o pins (connect a resonator.) 8-bit i/o port with the same function as port p0 cmos compatible input level cmos 3-state output structure 8-bit i/o port with the same function as port p0 cmos compatible input level. cmos 3-state output structure. 8-bit cmos i/o port with the same function as port p0 p7 0 p7 5 : cmos compatible input level or ttl compatible input level p7 6 , p7 7 : cmos compatible input level or smbus input level in the i 2 c-bus interface function, n-channel open-drain output structure each pin level of p7 0 to p7 5 can be read evev in output port mode. 8-bit cmos i/o port with the same function as port p0 cmos compatible input level. cmos 3-state output structure. i/o port p4 p4 2 /int 0 p4 3 /int 1 p4 4 /rxd p4 5 /txd p4 6 /s clk interrupt input pins serial i/o function pins p4 7 /s rdy /clkrun serial i/o function pins serialized irq function pin p5 6 /da 1 /pwm 01 p5 7 /da 2 /pwm 11 p5 0 /int 5 p5 1 /int 20 p5 2 /int 30 p5 3 /int 40 p5 4 /cntr 0 p5 5 /cntr 1 i/o port p5 interrupt input pins timer x, timer y function pins d-a converter output pins pwm output pins p6 0 /an 0 p6 7 /an 7 p7 0 p7 1 p7 2 p7 6 /s da p7 7 /s cl i/o port p6 i/o port p7 a-d converter output pins interrupt input pins i 2 c-bus interface function pins p7 3 /int 21 p7 4 /int 31 p7 5 /int 41 i/o port p8 p8 0 /lad 0 p8 1 /lad 1 p8 2 /lad 2 p8 3 /lad 3 p8 4 /lframe p8 5 /lreset p8 6 /lclk p8 7 /serirq serialized irq function pin lpc interface function pins
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 5 part numbering fig. 3 part numbering m3885 8 m c -xxx hp product name package type hp : 80p6q-a rom number omitted in the flash memory version. rom/flash memory size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; user cannot use those bytes. however, they can be programmed or erased in the flash memory version, so that the users can use them. memory type m f : mask rom version : flash memory version ram size 0 1 2 3 4 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes 9: 36864 bytes a: 40960 bytes b: 45056 bytes c: 49152 bytes d: 53248 bytes e: 57344 bytes f: 61440 bytes 5 6 7 8 9 : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 6 group expansion mitsubishi plans to expand the 3885 group as follows. memory type support for mask rom, flash memory version. memory size rom size ........................................................... 32 k to 60 k bytes ram size .......................................................... 1024 to 2048 bytes packages 80p6q-a .................................. 0.5 mm-pitch plastic molded lqfp fig. 4 memory expansion plan ram size (bytes) remarks package table 3 products plan list product name as of may 2002 32768 (32638) 49152 (19022) 32768 (32638) 61440 (p) rom size (bytes) rom size for user in ( ) memory expansion m38857m8-xxxhp m38858mc-xxxhp M38859M8-XXXHP m38859ffhp 1024 1536 2048 2048 80p6q-a mask rom version flash memory version m38857m8 60k rom size (bytes) 56k 48k 40k 32k 24k 16k 8k 256 512 768 1024 1280 1536 1792 2048 rom external ram size (bytes) m38858mc m38859ff m38859m8
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7 functional description central processing unit (cpu) the 3885 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. fig. 5 740 family cpu register structure [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 7. store registers other than those described in figure 7 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 8 table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r on-going routin e m (s) (pc h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) (s) (s) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) (s) (s) 1 (s) (s) + 1 i n t e r r u p t s e r v i c e r o u t i n e pop contents of processor status register from stack m (s) (pc h ) (s) (s) 1 m (s) (pc l ) (s) (s) 1 (pc l )m (s) (s) (s) + 1 (s) (s) + 1 (pc h )m (s) pop return address from stack i flag is set from 0 to 1 fetch the jump vector push return address on stack push contents of processor status register on stack i n t e r r u p t r e q u e s t ( n o t e ) interrupt disable flag is 0
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 9 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 10 [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : n o t a v a i l a b l e 1 0 : n o t a v a i l a b l e 1 1 : n o t a v a i l a b l e p o r t p 4 0 / p 4 1 s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e f i x t h i s b i t t o 1 . 1
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 11 memory ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom rom is used for program code and data table storage. the first 128 bytes and the last 2 bytes of rom are reserved for device testing code and the rest is user area. programming/eras- ing of the reserved rom area is possible in the flash memory version. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. interrupt vector area the interrupt vector area contains reset and interrupt vectors. special function register (sfr) area the special function register area contains the control registers such as i/o ports, timers, serial i/o, etc. fig. 8 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 3 2 7 6 8 4 9 1 5 2 6 1 4 4 0 8 0 0 0 1 6 4 0 0 0 1 6 1 0 0 0 1 6 8 0 8 0 1 6 4 0 8 0 1 6 1 0 8 0 1 6 y y y y 1 6 zzzz 16 r a m rom 1 0 2 4 1 5 3 6 2 0 4 8 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 0ff0 16 0 f f f 1 6 s f r a r e a not used i n t e r r u p t v e c t o r a r e a r e s e r v e d r o m a r e a ( n o t e ) ( 1 2 8 b y t e s ) z e r o p a g e special page r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 reserved rom area (note) r o m a r e a r o m s i z e ( b y t e s ) a d d r e s s y y y y 1 6 a d d r e s s z z z z 1 6 sfr area notes: this area is reserved in the mask rom version. this area is usable in flash memory version.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 12 fig. 9 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 0 0 2 f 1 6 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0012 16 0013 16 0 0 1 4 1 6 0 0 1 5 1 6 0016 16 0017 16 0 0 1 8 1 6 0 0 1 9 1 6 001a 16 001b 16 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 001f 16 s e r i a l i z e d i r q r e q u e s t r e g i s t e r ( s e r i r q ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) port p8 (p8)/port p4 input register (p4i) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) baud rate generator (brg) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n r e g i s t e r 1 ( a d 1 ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) ad/da control register (adcon) d - a 1 c o n v e r s i o n r e g i s t e r ( d a 1 ) d-a2 conversion register (da2) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) interrupt request register 1 (ireq1) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) i 2 c status register (s1) i 2 c control register (s1d) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) d a t a b a s b u f f e r r e g i s t e r 0 ( d b b 0 ) d a t a b a s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s t s 0 ) l p c c o n t r o l r e g i s t e r ( l p c c o n ) d a t a b a s b u f f e r r e g i s t e r 1 ( d b b 1 ) d a t a b a s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s t s 1 ) c o m p a r a t o r d a t a r e g i s t e r ( c m p d ) p o r t c o n t r o l r e g i s t e r 1 ( p c t l 1 ) p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) p w m 0 h r e g i s t e r ( p w m 0 h ) p w m 0 l r e g i s t e r ( p w m 0 l ) pwm1h register (pwm1h) pwm1l register (pwm1l) a-d conversion register 2 (ad2) i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) 0ff8 16 0ff9 16 port p8 direction register (p8d)/port p7 input register (p7i) 0 f f 0 1 6 0ff1 16 0ff2 16 0ff3 16 lpc0 address register l (lpc0adl) l p c 0 a d d r e s s r e g i s t e r h ( l p c 0 a d h ) l p c 1 a d d r e s s r e g i s t e r l ( l p c 1 a d l ) lpc1 address register h (lpc1adh) s e r i a l i z e d i r q c o n t r o l r e g i s t e r ( s e r c o n ) 0ffe 16 p o r t p 5 i n p u t r e g i s t e r ( p 5 i ) p o r t c o n t r o l r e g i s t e r 3 ( p c t l 3 ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f m c r ) 0fff 16 reserved (note) (note) n o t e : t h i s a p p l i e s t o o n l y f l a s h m e m o r y v e r s i o n .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 13 pin name input/output i/o structure non-port function ref.no. table 6 i/o port function (1) related sfrs i/o ports all i/o pins are programmable as input or output. all i/o ports have direction registers which specify the data direction of each pin like input/output. one bit in a direction register corresponds to one pin. each pin can be set to be input or output port. writing 0 to the bit corresponding to the pin, that pin becomes an input mode. writing 1 to the bit, that pin becomes an output mode. when the data is read from the bit of the port register correspond- ing to the pin which is set to output, the value shows the port latch data, not the input level of the pin. when a pin set to input, the pin comes floating. in input port mode, writing the port register changes only the data of the port latch and the pin remains high impedance state. when the p8 function selection bit of the port control register 2 is set to 1 , reading from address 0010 16 reads the port p4 register, and reading from address 0011 16 reads the port p7 register. especially, the input level of p4 2 to p4 6 pins and p7 0 to p7 5 pins can be read regardless of the data of the direction registers in this case. p0 0 -p0 7 p1 0 p1 7 p2 0 /cmp ref port p0 port p1 cmos compatible input level cmos 3-state output or n-channel open- drain output analog comparator power source input pin port control register 1 (1) (2) port control register 1 port control register 2 p2 1 p2 7 p3 0 /pwm 00 p3 1 /pwm 10 port p2 cmos compatible input level cmos 3-state output (3) (4) (5) port control register 1 ad/da control register pwm output key-on wake up input comparator input p3 2 p3 7 port p3 (6) key-on wake up input comparator input port control register 1 p4 0 /x cout p4 1 /x cin p4 2 /int 0 p4 3 /int 1 p4 4 /r x d input/output, individual bits (7) (8) (9) (10) (11) sub-clock generating circuit cpu mode register external interrupt input interrupt edge selection register port control register 2 serial i/o control register port control register 2 serial i/o function input p4 5 /t x d port p4 cmos compatible input level cmos 3-state output or n-channel open- drain output (12) serial i/o control register uart control register port control register 2 serial i/o function output p4 6 /s clk (13) serial i/o control register port control register 2 serial i/o function i/o p4 7 /s rdy /clkrun serial i/o control register serialized irq control register serial i/o function output serialized irq function output (14)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 14 notes1 : for details usage of double-function ports as function i/o ports, refer to the applicable sections. 2 : make sure that the input level of each pin should be either 0 v or v cc in stp mode. when an input level is at an intermediate voltage level, the i cc current will become large because of the input buffer gate. pin name input/output i/o format non-port function ref.no. table 7 i/o port function (2) related sfrs p5 0 /int 5 port p5 port p6 port p7 port p8 input/output, individual bits cmos compatible input level cmos 3-state output or n-channel opendrain output cmos compatible input level cmos 3-state output cmos compatible input level or ttl input level pure n-channel open-drain output cmos compatible input level or smbus input level pure n-channel open-drain output cmos compatible input level cmos 3-state output external interrupt input interrupt edge selection register (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) p5 1 /int 20 p5 2 /int 30 p5 3 /int 40 p5 4 /cntr 0 p5 5 /cntr 1 timer x, timer y func- tion i/o timer xy mode register p5 6 /da 1 / pwm 01 p5 7 /da 2 / pwm 11 d-a converter output pwm output ad/da control register uart control register p6 0 /an 0 p6 7 /an 7 a-d converter input ad/da control register p7 0 p7 1 p7 2 port control register 2 p7 3 /int 21 p7 4 /int 31 p7 5 /int 41 external interrupt input interrupt edge selection register port control register 2 p7 6 /s da p7 7 /s cl i 2 c-bus interface func- tion i/o i 2 c control register p8 0 /lad 0 p8 1 /lad 1 p8 2 /lad 2 p8 3 /lad 3 p8 4 / lframe p8 5 / lreset p8 6 /lclk p8 7 / serirq lpc interface function i/o data bus buffer control register serialized irq function i/o
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 15 fig. 10 port block diagram (1) ( 1 ) p o r t s p 0 , p 1 d a t a b u s p o r t l a t c h p 0 0 p 0 3 , p 0 4 p 0 7 , p 1 0 p 1 3 , p 1 4 p 1 7 o u t p u t s t r u c t u r e s e l e c t i o n b i t s d i r e c t i o n r e g i s t e r ( 2 ) p o r t p 2 0 d a t a b u s p o r t l a t c h c o m p a r a t o r r e f e r e n c e p o w e r s o u r c e i n p u t c o m p a r a t o r r e f e r e n c e i n p u t p i n s e l e c t b i t ( 3 ) p o r t p2 1 p 2 7 d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ( 4 ) p o r t s p 3 0 , p 3 1 comparator input key-on wake-up input p 3 0 p 3 3 p u l l - u p c o n t r o l b i t d a t a b u s p o r t l a t c h pwm 00 (pwm 10 ) output p w m 0 ( p w m 1 ) o u t p u t p i n s e l e c t i o n b i t pwm 0 (pwm 1 ) enable bi t direction register (7) port p4 1 s u b - c l o c k o s c i l l a t i o n c i r c u i t p o r t x c s w i t c h b i t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t x c s w i t c h b i t ( 6 ) p o r t p 4 0 port x c switch bit sub-clock oscillation circuit port p4 1 d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ( 5 ) p o r t s p 3 2 p 3 7 p3 0 ?3 3 , p3 4 ?3 7 pull-up control bit d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ? 1 . r e a d i n g t h e p o r t p 8 r e g i s t e r ( a d d r e s s 0 0 1 0 1 6 ) i s s w i t c h e d t o p o r t p 4 p i n i n p u t l e v e l b y t h e p 8 f u n c t i o n s e l e c t i o n b i t o f t h e p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) . (8) ports p4 2 , p4 3 p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t data bus port latch ? 1 d i r e c t i o n r e g i s t e r i n t e r r u p t i n p u t c o m p a r a t o r i n p u t key-on wake-up input d i r e c t i o n r e g i s t e r
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 16 (10) port p4 5 d a t a b u s s e r i a l i / o e n a b l e b i t t r a n s m i t e n a b l e b i t s e r i a l i / o o u t p u t p 4 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t p o r t l a t c h ? 1 s e r i a l i / o i n p u t ( 9 ) p o r t p 4 4 d a t a b u s s e r i a l i / o e n a b l e b i t r e c e i v e e n a b l e b i t p o r t l a t c h p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t ? 1 ( 1 1 ) p o r t p 4 6 data bu s serial i/o clock output serial i/o external clock input p o r t l a t c h p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t serial i/o enable bit serial i/o mode selection bi t serial i/o enable bi t ? 1 (13) ports p5 0 to p5 3 i n t e r r u p t i n p u t data bu s port latch (14) ports p5 4 , p5 5 port latch data bu s pulse output mode timer output c n t r 0 , c n t r 1 i n t e r r u p t i n p u t (15) ports p5 6 , p5 7 d - a c o n v e r t e r o u t p u t d-a 1 (d-a 2 ) output enable bit data bu s p o r t l a t c h p w m 0 1 ( p w m 1 1 ) o u t p u t p w m 0 ( p w m 1 ) o u t p u t p i n s e l e c t i o n b i t p w m 0 ( p w m 1 ) e n a b l e b i t (16) port p6 a n a l o g i n p u t p i n s e l e c t i o n b i t a-d converter input data bu s p o r t l a t c h ? 1 . r e a d i n g t h e p o r t p 8 r e g i s t e r ( a d d r e s s 0 0 1 0 1 6 ) i s s w i t c h e d t o p o r t p 4 p i n i n p u t l e v e l b y t h e p 8 f u n c t i o n s e l e c t i o n b i t o f t h e p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) . (12) port p4 7 data bu s serial i/o ready output p o r t l a t c h clkrun output serial i/o mode selection bi t serial i/o enable bi t s rdy output enable bi t serialized irq enable bit p 5 i o p e n d r a i n s e l e c t i o n b i t direction register direction register d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r fig. 11 port block diagram (2)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 17 ? 2. t h e i n p u t l e v e l c a n b e s w i t c h e d b e t w e e n c m o s c o m p a t i b l e i n p u t l e v e l a n d t t l l e v e l b y t h e p 7 i n p u t l e v e l s e l e c t i o n b i t o f t h e p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) . r e a d i n g t h e p o r t p 8 d i r e c t i o n r e g i s t e r i s s w i t c h e d t o p o r t p 7 p i n i n p u t l e v e l b y t h e p 8 f u n c t i o n s e l e c t i o n b i t o f t h e p o r t c o n t r o l r e g i s t e r 2 ( p c t l 2 ) . ? 3. t h e i n p u t l e v e l c a n b e s w i t c h e d b e t w e e n c m o s c o m p a t i b l e i n p u t l e v e l a n d s m b u s l e v e l b y t h e i 2 c - b u s i n t e r f a c e p i n i n p u t s e l e c t i o n b i t o f t h e i 2 c c o n t r o l r e g i s t e r ( s i d ) . (18) ports p7 3 to p7 5 data bu s p o r t l a t c h d i r e c t i o n r e g i s t e r i n t e r r u p t i n p u t ? 2 ( 1 9 ) p o r t p 7 6 d a t a b u s port latch d i r e c t i o n r e g i s t e r s da output s d a i n p u t ? 3 i 2 c - b u s i n t e r f a c e e n a b l e b i t (20) port p7 7 i 2 c-bus interfac e enable bi t s c l o u t p u t s cl input ? 3 d i r e c t i o n r e g i s t e r port latch d a t a b u s ( 2 1 ) p o r t s p 8 0 t o p 8 3 l a d [ 3 : 0 ] lpc enable bit data bus port latch direction register (22) ports p8 4 to p8 6 l r e s e t l c l k l f r a m e lpc enable bit data bus port latch direction register ( 2 3 ) p o r t p 8 7 i r q s e r s i r q e n a b l e b i t d a t a b u s port latch d i r e c t i o n r e g i s t e r ( 1 7 ) p o r t s p 7 0 t o p 7 2 d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ? 2 fig. 12 port block diagram (3)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 18 port control register 1 b 7b 0 port control register 2 p0 0 p0 3 output structure selection bit 0: cmos 1: n-channel open-drain p0 4 p0 7 output structure selection bit 0: cmos 1: n-channel open-drain p1 0 p1 3 output structure selection bit 0: cmos 1: n-channel open-drain p1 4 p1 7 output structure selection bit 0: cmos 1: n-channel open-drain p3 0 p3 3 pull-up control bit 0: no pull-up 1: pull-up p3 4 p3 7 pull-up control bit 0: no pull-up 1: pull-up pwm 0 enable bit 0: pwm 0 output disabled 1: pwm 0 output enabled pwm 1 enable bit 0: pwm 1 output disabled 1: pwm 1 output enabled n o t u s e d ( r e t u r n s 0 w h e n r e a d ) p 7 i n p u t l e v e l s e l e c t i o n b i t ( p 7 0 - p 7 5 ) 0 : c m o s i n p u t l e v e l 1 : t t l i n p u t l e v e l p 4 o u t p u t s t r u c t u r e s e l e c t i o n b i t ( p 4 2 , p 4 3 , p 4 4 , p 4 6 ) 0 : c m o s 1 : n - c h a n n e l o p e n - d r a i n p 8 f u n c t i o n s e l e c t i o n b i t 0 : p o r t p 8 / p o r t p 8 d i r e c t i o n r e g i s t e r 1 : p o r t p 4 i n p u t r e g i s t e r / p o r t p 7 i n p u t r e g i s t e r i n t 2 , i n t 3 , i n t 4 i n t e r r u p t s w i t c h b i t 0 : i n t 2 0 , i n t 3 0 , i n t 4 0 i n t e r r u p t 1 : i n t 2 1 , i n t 3 1 , i n t 4 1 i n t e r r u p t t i m e r y c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 1 : f ( x c i n ) o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : a u t o m a t i c s e t 0 1 1 6 t o t i m e r 1 a n d f f 1 6 t o p r e s c a l e r 1 2 1 : n o a u t o m a t i c s e t c o m p a r a t o r r e f e r e n c e i n p u t s e l e c t i o n b i t 0 : p 2 0 / c m p r e f i n p u t 1 : r e f e r e n c e i n p u t f i x e d b7 b0 ( p c t l 1 : a d d r e s s 0 0 2 e 1 6 ) ( p c t l 2 : a d d r e s s 0 0 2 f 1 6 ) fig. 13 structure of port i/o related registers (1)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 19 p o r t p 5 i n p u t r e g i s t e r b 7b0 p o r t c o n t r o l r e g i s t e r 3 p 5 0 i n p u t l e v e l b i t p 5 1 i n p u t l e v e l b i t p 5 2 i n p u t l e v e l b i t p 5 3 i n p u t l e v e l b i t t h e s e b i t s d i r e c t l y s h o w t h e p i n i n p u t l e v e l s . 0 : l l e v e l i n p u t 1 : h l e v e l i n p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) b 7b0 ( p 5 i : a d d r e s s 0 f f 8 1 6 ) ( p c t l 3 : a d d r e s s 0 f f 9 1 6 ) p 5 0 o p e n d r a i n s e l e c t i o n b i t p 5 1 o p e n d r a i n s e l e c t i o n b i t p 5 2 o p e n d r a i n s e l e c t i o n b i t p 5 3 o p e n d r a i n s e l e c t i o n b i t 0 : c m o s 1 : n - c h a n n e l o p e n d r a i n n o t u s e d ( r e t u r n s 0 w h e n r e a d ) fig. 14 structure of port i/o related registers (2)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 20 interrupts interrupts occur by 16 sources among 22 sources: thirteen exter- nal, nine internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt caused by the brk instruction. an interrupt occurs when both the corresponding interrupt request bit and interrupt enable bit are 1 and the interrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction interrupt cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are serviced according to the priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table and stored into the program counter. interrupt source selection any of the following interrupt sources can be selected by the inter- rupt source selection register (intsel). 1. int 0 or input buffer full 2. int 1 or output buffer empty 3. serial i/o receive or lreset 4. serial i/o transmission or s cl s da 5. timer 2 or int 5 6. cntr 0 or int 0 7. cntr 1 or int 1 8. a-d conversion or key-on wake-up external interrupt pin selection the external interrupt sources of int 2 , int 3 , and int 4 can be se- lected from either input pin from int 20 , int 30 , int 40 or input pin from int 21 , int 31 , int 41 by the int 2 , int 3 , int 4 interrupt switch bit (bit 4 of pctl2). notes when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ); timer xy mode register (address 0023 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt source selection register (address 0039 16 ) when setting input pin of external interrupts int 2 , int 3 and int 4 related register: int 2 , int 3 , int 4 interrupt switch bit of p ort con- trol register 2 (bit 4 of address 002f 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the active edge selection bit or the interrupt source selec- tion bit to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled).
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 21 interrupt request generating conditions remarks interrupt source low fffc 16 high priority table 8 interrupt vector addresses and priority vector addresses (note 1) reset (note 2) int 0 input buffer full (ibf) int 1 output buffer empty (obe) at reset at detection of either rising or falling edge of int 0 input at input data bus buffer writing at detection of either rising or falling edge of int 1 input at output data bus buffer read- ing non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) serial i/o reception at completion of serial i/o data reception valid when serial i/o is selected serial i/o transmission s cl , s da timer x timer y timer 1 timer 2 at completion of serial i/ otransfer shift or when trans- mission buffer is empty at detection of either rising or falling edge of s cl or s da at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow valid when serial i/o is selected external interrupt (active edge selectable) stp release timer underflow lreset at falling edge of lreset input external interrupt 1 2 3 4 5 6 cntr 0 int 0 cntr 1 int 1 at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of cntr 1 input at detection of either rising or falling edge of int 1 input external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) int 5 at detection of either rising or falling edge of int 5 input external interrupt (active edge selectable) 7 8 9 10 i 2 c int 2 at completion of data transfer at detection of either rising or falling edge of int 2 input external interrupt (active edge selectable) 11 12 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset functions in the same way as an interrupt with the highest priority. int 3 int 4 a-d converter key-on wake-up brk instruction at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at completion of a-d conversion at falling of port p3 (at input) in- put logical level and at brk instruction execution external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) non-maskable software interrupt 13 14 15 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffed 16 17 ffef 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 22 fig. 15 interrupt control fig. 16 structure of interrupt-related registers (1) i n t e r r u p t d i s a b l e f l a g ( i ) interrupt request interrupt request bi t i n t e r r u p t e n a b l e b i t brk instruction rese t 0 : no interrupt request issued 1 : interrupt request issued interrupt request register 2 cntr 0 /int 0 interrupt request bit cntr 1 /int 1 interrupt request bit i 2 c interrupt request bit int 2 interrupt request bit int 3 interrupt request bit int 4 interrupt request bit ad converter/key-on wake-up interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 /int 0 interrupt enable bit cntr 1 /int 1 interrupt enable bit i 2 c interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit int 4 interrupt enable bit ad converter/key-on wake-up interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) interrupt edge selection register int 0 active edge selection bit int 1 active edge selection bit not used (returns 0 when read) int 2 active edge selection bit int 3 active edge selection bit int 4 active edge selection bit int 5 active edge selection bit not used (returns 0 when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 /input buffer full interrupt request bit int 1 /output buffer empty interrupt request bit serial i/o receive interrupt/lreset request bit serial i/o transmit/s cl , s da interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2/int 5 interrupt request bit interrupt control register 1 int 0 /input buffer full interrupt enable bit int 1 /output buffer empty interrupt enable bit serial i/o receive interrupt/lreset enable bit serial i/o transmit/s cl , s da interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2/int 5 interrupt enable bit (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 0
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 23 b 7 int 0 /input buffer full interrupt source selection bit 0 : int 0 interrupt 1 : input buffer full interrupt int 1 /output buffer empty interrupt source selection bit 0 : int 1 interrupt 1 : output buffer empty interrupt serial i/o receive/lreset interrupt source selection bit 0 : serial i/o receive 1 : lreset interrupt serial i/o transmit/s cl , s da interrupt source selection bit 0 : serial i/o transmit interrupt 1 : s cl , s da interrupt timer 2/int 5 interrupt source selection bit 0 : timer 2 interrupt 1 : int 5 interrupt cntr 0 /int 0 interrupt source selection bit 0 : cntr 0 interrupt 1 : int 0 interrupt cntr 1 /int 1 interrupt source selection bit 0 : cntr 1 interrupt 1 : int 1 interrupt ad converter/key-on wake-up interrupt source selection bit 0 : a-d converter interrupt 1 : key-on wake-up interrupt i n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( i n t s e l : a d d r e s s 0 0 3 9 1 6 ) b 0 fig. 17 structure of interrupt-related registers (2)
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 24 fig. 18 connection example when using key input interrupt and port p3 block diagram ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? p o r t p 3 0 l a t c h p o r t p 3 0 d i r e c t i o n r e g i s t e r = 0 port p3 1 latch p o r t p 3 1 d i r e c t i o n r e g i s t e r = 0 port p3 2 latch p o r t p 3 2 d i r e c t i o n r e g i s t e r = 0 port p3 3 latch port p3 3 direction register = 0 p o r t p 3 4 l a t c h p o r t p 3 4 d i r e c t i o n r e g i s t e r = 1 p o r t p 3 5 l a t c h port p3 5 direction register = 1 p o r t p 3 6 l a t c h port p3 6 direction register = 1 p o r t p 3 7 l a t c h port p3 7 direction register = 1 p 3 0 i n p u t p 3 1 i n p u t p3 2 input p3 3 input p 3 4 o u t p u t p 3 5 o u t p u t p 3 6 o u t p u t p 3 7 o u t p u t p o r t c o n t r o l r e g i s t e r 1 b i t 5 = 0 port p3 input circuit comparator circuit p o r t p x x l l e v e l o u t p u t ? p-channel transistor for pull-up ?? cmos output buffer k e y i n p u t i n t e r r u p t r e q u e s t p o r t c o n t r o l r e g i s t e r 1 b i t 4 = 1 key input interrupt (key-on wake up) a key input interrupt request is generated by applying l level to any pin of port p3 that have been set to input mode. in other words, it is generated when the logical and of all port p3 input goes from 1 to 0 . an example of using a key input interrupt is shown in figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p3 0 p3 3 .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 25 timers the 3885 group has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down structure. when the timer reaches ?0 16 ? an underflow occurs at the next count pulse and the corre- sponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit cor- responding to that timer is set to ?? timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency di- vided by 16. the output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts f(x in )/16. (2) pulse output mode timer x (or timer y) counts f(x in )/16. whenever the contents of the timer reach ?0 16 ? the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge se- lection bit is ?? output begins at ?h? if it is ?? output starts at ?? when using a timer in this mode, set the corresponding port p5 4 ( or port p5 5 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is ?? the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is ?? the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is ?? the timer counts f(x in )/16 while the cntr 0 (or cntr 1 ) pin is at ?? if the cntr 0 (or cntr 1 ) active edge selection bit is ?? the timer counts while the cntr 0 (or cntr 1 ) pin is at ?? the count can be stopped by setting ??to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer overflows. the count source for timer y in the timer mode or the pulse output mode can be selected from either f(x in )/16 or f(x cin ) by the timer y count source selection bit of the port control register 2 (bit 5 of pctl2). fig. 19 structure of timer xy mode register t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p timer xy mode register (tm : address 0023 16 ) timer y operating mode bit b5b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 c n t r 0 a c t i v e e d g e s e l e c t i o n b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e b 0 t i m e r x o p e r a t i n g m o d e b i t b 1 b 0 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e timer y count stop bit 0: count start 1: count stop
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 26 fig. 20 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p 5 4 / c n t r 0 q q p 5 5 / c n t r 1 1 / 1 6 f ( x i n ) 0 1 r r 1 0 0 1 t t p r e s c a l e r x l a t c h ( 8 ) prescaler x (8) t i m e r x l a t c h ( 8 ) t i m e r x ( 8 ) t o t i m e r x i n t e r r u p t r e q u e s t b i t t o g g l e f l i p - f l o p t i m e r x c o u n t s t o p b i t p u l s e w i d t h m e a s u r e m e n t m o d e e v e n t c o u n t e r m o d e t o c n t r 0 i n t e r r u p t r e q u e s t b i t pulse output mode p o r t p 5 4 l a t c h p o r t p 5 4 d i r e c t i o n r e g i s t e r c n t r 0 a c t i v e e d g e s e l e c t i o n b i t timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) t i m e r y l a t c h ( 8 ) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode p o r t p 5 5 l a t c h port p5 5 direction register c n t r 1 a c t i v e e d g e s e l e c t i o n b i t t i m e r y l a t c h w r i t e p u l s e p u l s e o u t p u t m o d e timer mode pulse output mod e data bus d a t a b u s d i v i d e r o s c i l l a t o r prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) t i m e r 2 ( 8 ) to timer 2 interrupt request bit t o t i m e r 1 i n t e r r u p t r e q u e s t b i t c n t r 0 a c t i v e e d g e s e l e c t i o n b i t cntr 1 active edge selection bit pulse width measure- ment mode event counter mode 1/16 f(x in ) d i v i d e r o s c i l l a t o r 1 / 1 6 f ( x i n ) divider o s c i l l a t o r f ( x c i n ) o s c i l l a t o r 0 1 t i m e r y c o u n t s o u r c e s e l e c t i o n b i t ( f ( x c i n ) i n l o w - s p e e d m o d e ) (f(x cin ) in low-speed mode) (f(x cin ) in low-speed mode)
27 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. basic operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (wdtcon) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an op- tional value into the watchdog timer control register (wdtcon) and an internal reset occurs at an underflow of the watchdog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (wdtcon) may be started be- fore an underflow. when the watchdog timer control register (wdtcon) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watchdog timer h count source selection bit are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (wdtcon), each watchdog timer h and l is set to ?f 16 ? fig. 22 structure of watchdog timer control register watchdog timer h count source selection bit operation bit 7 of wdtcon permits selecting a watchdog timer h count source. when this bit is set to ?? the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at f(x in )=8 mhz and 32.768 s at f(x cin )=32 khz . when this bit is set to ?? the count source becomes the signal divided by 16 for f(x in ) (or f(x cin ) in low speed mode). the detec- tion time in this case is set to 512 s at f(x in )=8 mhz and 128 ms at f(x cin )=32 khz . this bit is cleared to ??after resetting. stp instruction disable bit bit 6 of wdtcon permits disabling the stp instruction when the watchdog timer is in operation. when this bit is ?? the stp instruction is enabled. when this bit is ?? the stp instruction is disabled. when this bit is ?? the stp instruction execution cause an inter- nal reset. when this bit is set to ?? it cannot be rewritten to ??by program. this bit is cleared to ??after resetting. fig. 21 block diagram of watchdog timer x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either hi g h-s p eed, middle-s p eed or low-s p eed mode is selected b y bits 7 and 6 of the cpu mode re g ister. stp instruction ff 16 is set when watchdog timer control register is written to. b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 001e 16 ) b 7
28 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pulse width modulation (pwm) output circuit the 3885 group has two pwm output circuits, pwm0 and pwm1, with 14-bit resolution respectively. these can operate indepen- dently. when the oscillation frequency x in is 8 mhz, the minimum fig. 23 pwm block diagram (pwm0) resolution bit width is 250 ns and the cycle period is 4096 s. the pwm timing generator supplies a pwm control signal based on a signal that is the frequency of the x in clock. the following explanation assumes f(x in ) = 8 mhz. 14 1/2 pwm 0 enable bit p3 0 latch p3 0 /pwm 00 pwm0l register (address 0031 16 ) pwm0h register (address 0030 16 ) bit 7 bit 0 bit 5 msb lsb pwm 0 bit 7 bit 0 pwm0 timing generator (64 s period) (4096 s period) pwm0 latch (14 bits) set to 1 at write data bus f(x in ) (8mhz) 14-bit pwm0 circuit p5 6 direction re g ister pwm 0 enable bit pwm 0 enable bit p5 6 latch p5 6 /da 1 /pwm 01 pwm 0 output selection bit p3 0 direction register (4mhz) pwm 0 enable bit pwm 0 output selection bit
29 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers data setup (pwm0) the pwm0 output pin also functions as port p3 0 or p5 6 . the pwm0 output pin is selected from either p3 0 /pwm 00 or p5 6 /pwm 01 by pwm 0 output pin selection bit (bit 4 of adcon). the pwm0 output becomes enabled state by setting pwm 0 en- able bit (bit 6 of pctl1). the high-order eight bits of output data are set in the pwm0h register and the low-order six bits are set in the pwm0l register. pwm1 is set as the same way. pwm operation the 14-bit pwm data is divided into the low-order six bits and the high-order eight bits in the pwm latch. the high-order eight bits of data determine how long an h -level signal is output during each sub-period. there are 64 sub-periods in each period, and each sub-period is 256 ? (64 s) long. the signal is h for a length equal to n times , where is the mini- mum resolution (250 ns). h or l of the bit in the add part shown in figure 24 is added to this h duration by the contents of the low-order 6-bit data ac- cording to the rule in table 9. that is, only in the sub-period tm shown by table 9 in the pwm cycle period t = 64t, its h duration is lengthened to the minimum resolution added to the length of other periods. for example, if the high-order eight bits of the 14-bit data are 03 16 and the low-order six bits are 05 16 , the length of the h -level out- put in sub-periods t 8 , t 24 , t 32 , t 40 , and t 56 is 4 , and its length is 3 in all other sub-periods. time at the h level of each sub-period almost becomes equal, because the time becomes length set in the high-order 8 bits or becomes the value plus , and this sub-period t (= 64 s, approxi- mate 15.6 khz) becomes cycle period approximately. transfer from register to latch data written to the pwml register is transferred to the pwm latch at each pwm period (every 4096 s), and data written to the pwmh register is transferred to the pwm latch at each sub-period (every 64 s). the signal which is output to the pwm output pin is corresponding to the contents of this latch. when the pwml reg- ister is read, the latch contents are read. however, bit 7 of the pwml register indicates whether the transfer to the pwm latch is completed; the transfer is completed when bit 7 is 0 and it is not done when bit 7 is 1 . table 9 relationship between low-order 6 bits of data and period set by the add bit low-order 6 bits of data (pwml) lsb 000000 000001 000010 000100 001000 010000 100000 sub-periods tm lengthened (m=0 to 63) none m=32 m=16, 48 m=8, 24, 40, 56 m=4, 12, 20, 28, 36, 44, 52, 60 m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63 fig. 24 pwm timing 4096 s 64 s 64 s 64 s 64 s 64 s m=0 m=7 m=9 m=63 m=8 15.75 s 15.75 s 15.75 s 16.0 s 15.75 s 15.75 s 15.75 s pulse width modulation register h pulse width modulation register l sub-periods where h pulse width is 16.0 s : sub-periods where h pulse width is 15.75 s : : 00111111 : 000101 m = 8, 24, 32, 40, 56 m = all other values
30 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 25 14-bit pwm timing (pwm 0 ) 6 a6 a6 a6 a6a 6 b6 a6 a6 a6 a6 a6 a6 a6a 6 b6 b6 b6 b6 b6 b6b6 b6b 6b6 b6 b6 b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 a 6 a 6 b 6b 6 b 6 a 6b 6b 6b 6 a 6 b 6b 6 b 6 a 6 a 6 a 6 a 6 a 6 a 6a 6a 6 a 6 a 6 a 6 a 6 a 6 a 4 3 4 4 3 4 4 3 4 6b 6a 69 68 67 02 01 6a 69 68 67 02 01 0 2 0 1 0 0 f f fe f d 97 9 6 95 02 0 1 00 f c ff f e f d 9 7 96 9 5 fc a d d a d d 1 6 5 3 1 6 1 a 9 3 1 6 1 a a 4 1 6 1aa4 16 1 e e 4 1 6 1 e f 5 1 6 t = 4096 s t = 64 s w h e n b i t 7 o f p w m 0 l i s 0 , t r a n s f e r f r o m r e g i s t e r t o l a t c h i s d i s a b l e d . 1 3 1 6 a4 16 2 4 1 6 35 16 7 b 1 6 6a 16 5 9 1 6 data 24 16 stored at address 0031 16 data 6a 16 stored at address 0030 16 data 7b 16 stored at address 0030 16 data 35 16 stored at address 0031 16 t r a n s f e r f r o m r e g i s t e r t o l a t c h t r a n s f e r f r o m r e g i s t e r t o l a t c h bit 7 cleared after transfer 6b 16 36 times 6a 16 28 times ( 1 0 7 ) ( 1 0 6 ) 6 b 1 6 2 4 t i m e s 6a 16 40 times t = 6 4 s (256 ? 0.25 s) m i n i m u m r e s o l u t i o n b i t w i d t h = 0 . 2 5 s h duration length specified by pwm0h 256 (64 s), fixed t h e a d d p o r t i o n s w i t h a d d i t i o n a l a r e d e t e r m i n e d b y p w m l . pwm0h register pwm0l register p w m 0 l a t c h ( 1 4 b i t s ) e x a m p l e 1 pwm 0 output h l 6 a 1 6 , 2 4 1 6 example 2 pwm 0 output l o w - o r d e r 6 - b i t o u t p u t : h l 6a 16 , 18 16 pwm output 8 - b i t c o u n t e r 1 0 6 ? 6 4 + 2 4 1 2 b 5 1 6 106 ? 64 + 36 2 ( 6 4 ? 6 4 s ) l o w - o r d e r 6 - b i t o u t p u t :
31 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o serial i/o serial i/o works as either clock synchronous serial i/o mode or universal asynchronous receiver transmitter (uart) serial i/o mode. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o control register (bit 6 of siocon) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. when an internal clock is used, the transfer starts by writing to the tb. fig. 26 block diagram of clock synchronous serial i/o fig. 27 operation of clock synchronous serial i/o function 1/4 1/4 f/f p4 6 /s clk serial i/o status register serial i/o control register p4 7 /s rdy /clkrun p4 4 /r x d p4 5 /t x d f(x in ) receive buffer register receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronous clock selection bit baud rate generator brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit data bus transmit shift register (f(x cin ) in low-speed mode) frequency division ratio 1/(n+1) address 0018 16 address 001a 16 address 001c 16 address 0018 16 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tsc = 1 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) txd pin rxd pin write pulse to transmit buffer register (tb) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and the next serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . s rdy pin
32 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode universal asynchronous transmitter receiver (uart) serial i/o mode can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. both the transmit and receive shift registers have a buffer, but the two buffers assigned the same address. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the re- ceive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 28 block diagram of uart mode f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) st/sp/pa generator transmit buffer register data bus transmit shift register transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) st detector sp detector uart control register character length selection bit brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p4 6 /s clk serial i/o status register p4 4 /r x d p4 5 /t x d (f(x cin ) in low-speed mode) address 0018 16 address 001a 16 address 001b 16 address 0019 16
33 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 29 operation of uart mode function [serial i/o control register (siocon)] 001a 16 the serial i/o control register consists of eight control bits for the serial i/o function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid in uart mode and set the data format of an data transfer. the poff bit (bit4) is always valid and define the output structure of the p4 5 /t x d pin. [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit (sioe, bit 7 of sidcon) also clears all the status flags, including the er- ror flags. bits 0 to 6 of the serial i/o status register are initialized to 0 at re- set, but if the transmit enable bit (te, bit 4 of siocon) has been set to 1 , the transmit shift completion flag (tsc, bit 2) and the transmit buffer empty flag (tbe, bit 0) become 1 . [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character length is 7 bits, the msb data stored in the receive buffer is 0 . [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled). tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1 , can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1 . 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? serial output t x d pin serial input r x d pin receive buffer read signal ?
34 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 30 structure of serial i/o control registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o status register serial i/o control register b0 b0 brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin 1: p4 7 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 to p4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 to p4 7 operate as serial i/o pins) (siosts : address 0019 16 ) (siocon : address 001a 16 ) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (uartcon : address 001b 16 )
35 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) table 10 multi-master i 2 c-bus interface functions item format communication mode system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 31 shows a block diagram of the multi-master i 2 c-bus in- terface and table 10 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to system clock . fig. 31 block diagram of multi-master i 2 c-bus interface ? : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. s cl clock frequency i 2 c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb noise elimination circuit serial data (s da ) address comparator b7 i 2 c data shift register b0 data control circuit system clock ( ) interrupt generating circuit interrupt request signal (i 2 cirq) b7 mst trx bb pin al aas ad0 lrb b0 s1 b7 b0 tiss 10bit sad als bc2 bc1 bc0 s1d bit counter bb circuit clock control circuit noise elimination circuit serial clock (s cl ) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s 0 s2 s0d al circuit es0 sis i 2 c start/stop condition control register sip ssc4ssc3 ssc2 ssc1 ssc0 i 2 c clock control register i 2 c status register s2d interrupt generating circuit interrupt request signal (s cl s da irq) stop selection stsp sel clk stp i 2 c clock control register
36 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c data shift register (s0)] 0012 16 the i 2 c data shift register (s0) is an 8-bit shift register to store re- ceive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the s cl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the s cl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 cycles of are required from the rising of the s cl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 s1d) of the i 2 c con- trol register is 1 . the bit counter is reset by a write instruction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (s1) are 1 , the s cl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled regardless of the es0 bit value. [i 2 c address register (s0d)] 0013 16 the i 2 c address register (s0d) consists of a 7-bit slave address and _______ a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received imme- diately after the start condition is detected. _________ ?it 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?its 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data transmitted from the master is compared these bits. fig. 32 structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb slave address i 2 c address register (s0d: address 0013 16 ) read/write bit b7 b0
37 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 11 set values of i 2 c clock control register and s cl frequency fig. 33 structure of i 2 c clock control register s cl frequency (at = 4 mhz, unit : khz) (note 1) setting value of ccr4 ccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 notes 1: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 cycles of in the standard clock mode, and fluctu- ates from 2 to +2 cycles of in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduc- tion. these are value when s cl clock synchronization by the synchro- nous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. 2: each value of s cl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3: the data formula of s cl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by set- ting the s cl frequency control bits ccr4 to ccr0. setting disabled setting disabled setting disabled 1000/ccr value (note 3) 34.5 33.3 32.3 500/ccr value (note 3) 17.2 16.6 16.1 333 250 400 (note 3) 166 (note 2) (note 2) 100 83.3 [i 2 c clock control register (s2)] 0016 16 the i 2 c clock control register (s2) is used to set ack control, s cl mode and s cl frequency. ?its 0 to 4: s cl frequency control bits (ccr0?cr4) these bits control the s cl frequency. refer to table 11. ?it 5: s cl mode specification bit (fast mode) this bit specifies the s cl mode. when this bit is set to 0 , the standard clock mode is selected. when the bit is set to 1 , the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) and high-speed mode (2 division main clock). ?it 6: ack bit (ack bit) this bit sets the s da status when an ack clock ? is generated. when this bit is set to 0 , the ack return mode is selected and s da goes to l at the occurrence of an ack clock. when the bit is set to 1 , the ack non-return mode is selected. the s da is held in the h status at the occurrence of an ack clock. however, when the slave address matches with the address data in the reception of address data at ack bit = 0 , the s da is au- tomatically made l (ack is returned). if there is a unmatch between the slave address and the address data, the s da is auto- matically made h (ack is not returned). ? ack clock: clock for acknowledgment ?it 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0 , the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1 , the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the s da at the occurrence of an ack clock (makes s da h ) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 0016 16 ) b7 b0 s cl frequency control bits refer to table 11. s cl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock
38 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 34 structure of i 2 c control register [i 2 c control register (s1d)] 0015 16 the i 2 c control register (s1d) controls data communication for- mat. ?its 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack bit (bit 7 of s2)) have been transferred, and bc0 to bc2 are re- turned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?it 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c bus interface. when this bit is set to 0 , the use disable status is provided, so that the s da and the s cl become high-impedance. when the bit is set to 1 , use of the interface is enabled. when es0 = 0 , the following is performed. pin = 1 , bb = 0 and al = 0 are set (which are bits of the i 2 c status register at s1 ). writing data to the i 2 c data shift register (s0) is disabled. ?it 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0 , the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register , bit 1) is re- ceived, transfer processing can be performed. when this bit is set to 1 , the free data format is selected, so that slave addresses are not recognized. ?it 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0 , the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (s0d) are compared with address data. when this bit is set to 1 , the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?it 6: system clock stop selection bit (clkstp) when executing the wit or stp instruction, this bit selects the condition of system clock provided to the multi-master i 2 c-bus in- terface. when this bit is set to 0 , system clock and operation of the multi-master i 2 c-bus interface stop by executing the wit or stp instruction. when this bit is set to 1 , system clock and operation of the multi- master i 2 c-bus interface do not stop even when the wit instruction is executed. when the system clock stop selection bit is 1 , do not execute the stp instruction. ?it 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the s cl and s da pins of the multi- master i 2 c-bus interface. b7 tiss clk stp 10 bit sad als es0 bc2 bc1 bc0 b0 system clock stop selection bit 0 : system clock stop when executing wit or stp instruction 1 : not system clock stop when executing wit instruction (do not use the stp instruction.) i 2 c control register (s1d : address 0015 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 00 0: 8 00 1: 7 01 0: 6 01 1: 5 10 0: 4 10 1: 3 11 0: 2 11 1: 1 i 2 c-bus interface enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus in p ut
39 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ?it 4: s cl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0 . at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0 , the s cl is kept in the 0 state and clock generation is disabled. figure 42 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: executing a write instruction to the i 2 c data shift register (s0). (this is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) when the es0 bit is 0 at reset when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?it 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0 , this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the s cl , s da pins in- put signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4 ssc0) of s2d. when the es0 bit (bit 3 of s1d) is 0 or reset, the bb flag is set to 0 . for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 0014 16 the i 2 c status register (s1) controls the i 2 c-bus interface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?it 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0 . if ack is not returned, this bit is set to 1 . except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (s0). ?it 1: general call detecting flag (ad0) when the als bit is 0 , this bit is set to 1 when a general call ? whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ? general call: the master transmits the general call address 00 16 to all slaves. ?it 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0 . ? in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (s0d). a general call is received. ? in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rwb bit), the first bytes agree. ? this bit is set to 0 by executing a write instruction to the i 2 c data shift register (s0) when es0 is set to 1 or reset. ?it 3: arbitration lost ? detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1 . at the same time, the trx bit is set to 0 , so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0 . the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ? arbitration lost : the status in which communication as a master is dis- abled.
40 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 36 interrupt request signal generating timing fig. 35 structure of i 2 c status register ?it 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0 , the reception mode is selected and the data of a transmitting device is received. when the bit is 1 , the transmis- sion mode is selected and address data and control data are output onto the s da in synchronization with the clock generated on the s cl . this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: when als is 0 in the slave reception mode or the slave transmission mode ___ when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: when arbitration lost is detected. when a stop condition is detected. when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . with mst = 0 and when a start condition is detected. with mst = 0 and when ack non-return is detected. at reset ?it 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0 , the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1 , the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. immediately after completion of 1-byte data transfer when arbi- tration lost is detected when a stop condition is detected. writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. s c l pin i 2 c i r q b7 mst b0 i 2 c status register (s1 : address 0014 16 ) last receive bit (note) 0 : last bit = 0 1 : last bit = 1 general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected scl pin low hold bit 0 : low hold 1 : release bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad0 lrb note: these bit and flags can be read out but cannot be written. write 0 to these bits at writing.
41 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers + 2 cycles (3.375 s) + 1 cycle < 4.0 s (3.25 s) fig. 39 start condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 39, 40, and table 14. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the s cl and s da pins satisfy three conditions: s cl re- lease time, setup time, and hold time (see table 14). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 14, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal i 2 cirq occurs to the cpu. table 14 start condition/stop condition detecting conditions note: unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at = 4 mhz. fig. 40 stop condition detecting timing diagram s cl release time standard clock mode high-speed clock mode 4 cycles (1.0 s) 2 cycles (1.0 s) 2 cycles (0.5 s) 3.5 cycles (0.875 s) ssc value 2 ssc value 2 ssc value 1 2 setup time hold time bb flag set/ reset time ssc value + 1 cycle (6.25 s) cycle < 4.0 s (3.0 s) start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (s1) at the same time after writing the slave address to the i 2 c data shift register (s0) with the condition in which the es0 bit of the i 2 c control register (s1d) and the bb flag are 0 , a start condition occurs. after that, the bit counter becomes 000 2 and an s cl for 1 byte is output. the start condition gen- erating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 37, the start condition generating timing diagram, and table 12, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (s1d) is 1 , write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c sta- tus register (s1) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 38, the stop condition generating timing diagram, and table 13, the stop condition generating timing table. fig. 37 start condition generating timing diagram fig. 38 stop condition generating timing diagram table 13 stop condition generating timing table item setup time start/stop condition generating selection bit 0 1 0 1 standard clock mode 5.5 s (22 cycles) 13.5 s (54 cycles) 5.5 s (22 cycles) 13.5 s (54 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 3.0 s (12 cycles) 7.0 s (28 cycles) 3.0 s (12 cycles) 7.0 s (28 cycles) table 12 start condition generating timing table item setup time start/stop condition generating selection bit standard clock mode note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 0 1 0 1 5.0 s (20 cycles) 13.0 s (52 cycles) 5.0 s (20 cycles) 13.0 s (52 cycles) 2.5 s (10 cycles) 6.5 s (26 cycles) 2.5 s (10 cycles) 6.5 s (26 cycles) hold time hold time i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e setup time s c l s da i 2 c status register write signal hold time s e t u p t i m e s cl s da h o l d t i m e setup time s cl s da bb flag s cl release time bb flag reset time h o l d t i m e setup time s c l s da b b f l a g s cl release time b b f l a g r e s e t t i m e
42 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [i 2 c start/stop condition control register (s2d)] 0017 16 the i 2 c start/stop condition control register (s2d) controls start/stop condition detection. bits 0 to 4: start/stop condition set bits (ssc4 ssc0) s cl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 14. do not set 00000 2 or an odd number to the start/stop condi- tion set bits (ssc4 to ssc0). refer to table 15, the recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency. bit 5: s cl /s da interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the s cl or s da pin. this bit selects the polarity of the s cl or s da pin interrupt pin. bit 6: s cl /s da interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the s cl pin and the s da pin. note: when changing the setting of the s cl /s da interrupt pin polarity se- lection bit, the s cl /s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the s cl /s da interrupt request bit may be set. when selecting the s cl /s da interrupt source, disable the inter- rupt before the s cl /s da interrupt pin polarity selection bit, the s cl / s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. bit 7: start/stop condition generating selection bit (stspsel) setup/hold time when the start/stop condition is generated can be selected. cycle number of system clock becomes standard for setup/hold time. additionally, setup/hold time is different between the start condition and the stp condition. (refer to tables 12 and 13.) set 1 to this bit when the system clock frequency is 4 mhz or more. address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. ? 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (s1d) to 0 . the first 7-bit address data transmitted from the master is compared with the high-order 7- bit slave address stored in the i 2 c address register (s0d). at the time of this comparison, address comparison of the rwb bit of the i 2 c address register (s0d) is not performed. for the data transmission format when the 7-bit addressing format is se- lected, refer to figure 42, (1) and (2). ? 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (s1d) to 1 . an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c ad- dress register (s0). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (s0) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (s1) is set to 1 . after the second-byte address data is stored into the i 2 c data shift reg- ister (s0), perform an address comparison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c address register (s0d) to 1 by soft- ware. this processing can make the 7-bit slave address and r/ ___ w data agree, which are received after a restart condition is detected, with the value of the i 2 c address register (s0d). for the data transmission format when the 10-bit addressing format is selected, refer to figure 42, (3) and (4).
43 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 42 address data communication format fig. 41 structure of i 2 c start/stop condition control register note: do not set 00000 2 or an odd number to the start/stop condition set bits (ssc4 to ssc0). table 15 recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency main clock divide ratio system clock (mhz) s cl release time ( s) setup time ( s) hold time ( s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.5 s (14 cycles) 3.25 s (13 cycles) 3.0 s (3 cycles) 3.5 s (7 cycles) 3.0 s (6 cycles) 3.0 s (3 cycles) 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) 3.25 s (13 cycles) 3.0 s (12 cycles) 2.0 s (2 cycles) 3.0 s (6 cycles) 2.5 s (5 cycles) 2.0 s (2 cycles) 4 1 2 1 b7 stsp sel b0 i 2 c start/stop condition control register start/stop condition set bits s cl /s da interrupt pin polarity selection bit 0 : falling edge active 1 : rising edge active s cl /s da interrupt pin selection bit 0 : s da valid 1 : s cl valid start/stop condition generating selection bit 0 : setup/hold time short mode 1 : setup/hold time long mode sis sip ssc4ssc3 ssc2 ssc1 ssc0 (s2d : address 0017 16 ) ss l a v e a d d r e s sr / w ad a t aa data a / a p 7 b i t s 0 1 t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s n m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s r / w ad a t aadata a p 7 b i t s 1 1 t o 8 b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r s s l a v e a d d r e s s 1 s t 7 b i t s r / w a 7 b i t s 0 8 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e s a d a t a ad a t a a / a p 1 t o 8 b i t s1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s r / w a 7 b i t s 0 8 b i t s ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e s adata a a s r s l a v e a d d r e s s 1 s t 7 b i t s r / w a data p s : s t a r t c o n d i t i o n a : a c k b i t s r : r e s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t 7 b i t s 1 1 to 8 bits 1 to 8 bits
44 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers example of master transmission an example of master transmission in the standard clock mode, at the s cl frequency of 100 khz and in the ack return mode is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (s0d) and 0 into the rwb bit. (2) set the ack return mode and s cl = 100 khz by setting 85 16 in the i 2 c clock control register (s2). (3) set 00 16 in the i 2 c status register (s1) so that transmission/ reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (s1d). (5) confirm the bus free condition by the bb flag of the i 2 c status register (s1). (6) set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (s0) and set 0 in the least significant bit. (7) set f0 16 in the i 2 c status register (s1) to generate a start condition. at this time, an s cl for 1 byte and an ack clock au- tomatically occur. (8) set transmit data in the i 2 c data shift register (s0). at this time, an s cl and an ack clock automatically occur. (9) when transmitting control data of more than 1 byte, repeat step (8). (10) set d0 16 in the i 2 c status register (s1) to generate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the s cl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (s0d) and 0 in the rwb bit. (2) set the no ack clock mode and s cl = 400 khz by setting 25 16 in the i 2 c clock control register (s2). (3) set 00 16 in the i 2 c status register (s1) so that transmission/ reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (s1d). (5) when a start condition is received, an address comparison is performed. (6) when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (s1) is set to 1 and an interrupt request signal occurs. when the transmitted address matches with the address set in (1): ass of the i 2 c status register (s1) is set to 1 and an interrupt request signal occurs. in the cases other than the above ad0 and aas of the i 2 c status register (s1) are set to 0 and no interrupt request sig- nal occurs. (7) set dummy data in the i 2 c data shift register (s0). (8) when receiving control data of more than 1 byte, repeat step (7). (9) when a stop condition is detected, the communication ends. (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. i 2 c data shift register (s0: address 0012 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. i 2 c address register (s0d: address 0013 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. i 2 c status register (s1: address 0014 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. i 2 c control register (s1d: address 0015 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. i 2 c clock control register (s2: address 0016 16 ) the read-modify-write instruction can be executed for this register. i 2 c start/stop condition control register (s2d: address 0017 16 ) the read-modify-write instruction can be executed for this register.
45 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ..... ..... ..... ..... ..... (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 5. lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch pro cess) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) busbusy: cli (interrupt enabled) 2. use branch on bit set of bbs 5, $0014, for the bb flag confirming and branch process. 3. use sta $12, stx $12 or sty $12 of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. disable interrupts during the following three process steps: bb flag confirming writing of slave address value trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 4.) execute the following procedure when the pin bit is 0 . ldm #$00, s1 (select slave receive mode) lda (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 ( trigger of restart condition generating ) cli (interrupt enabled) 2. select the slave receive mode when the pin bit is 0 . do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the s da pin is released. 3. the s cl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: writing of slave address value trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. it is because it may enter the state that the s cl pin is released and the s da pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1 . it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. (6) es0 bit switch in standard clock mode when ssc = 00010 2 or in high-speed clock mode, flag bb may switch to 1 if es0 bit is set to 1 when sda is l . countermeasure: set es0 to 1 when sda is h .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 46 lpc interface lpc interface function is base on low pin count (lpc) interface specification, revision 1.0. the 3885 supports only i/o read cycle and i/o write cycle. there are two channels of bus buffers to the host. the functions of input data bus buffer, output data bus buffer and data bus buffer status register are the same as that of the 8042, 3880 group, 3881 group and 3886 group. it can be written in or read out from the host controller through lpc interface. lpc in- terface function block diagram is shown in figure 43. functional input or output pins of lpc interface are shared with port 8 (p8 0 ?8 6 ). setting the lpc interface enable bit (bit3 of lpccon) to ??enables lpc interface. enabling channel i (i = 0, 1) of the data bus buffer is controlled by the data bus buffer i (i = 0, 1) enable bits (bit 4 or bit 5 of lpccon). the slave addresses of the data bus buffer channel i (i = 0, 1) are definable by setting lpci (i = 0, 1) address register h/l (lpc0adl, lpc0adh, lpc1adl, lpc1adh). the bit 2 value of lpci address register l is not decoded. this bit returns ??when the internal cpu read. the bit 2 of slave address is latched to xa2i flag when the host controller writes the data. the input buffer full (ibf) interrupt occurs when the host controller writes the data. the output buffer empty (obe) interrupt is gener- ated when the host controller reads out the data. the 3885 merges two input buffer full (ibf) interrupt requests and two output buffer empty (obe) interrupt requests as shown in figure 44. table 16 function explanation of the control pin in lpc interface p8 0 /lad 0 i/o these pins communicate address, control and data information between the host and the data bus buffer of the 3885. p8 1 /lad 1 i/o p8 2 /lad 2 i/o p8 3 /lad 3 i/o p8 4 /lframe i input the signal to indicate the start of new cycle and termination of abnormal communication cycles. i input the lpc synchronous clock signal. p8 5 /lreset i input the signal to reset the lpc interface function. pin name input/ output function p8 6 /lclk
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 47 fig. 43 block diagram of lpc interface function (1ch) input control circuit i n p u t d a t a b u s b u f f e r [ 7 : 4 ] lpc control register (lpccon) u 7 i u 6i u 5i u 4 i x a 2 iu 2i i b f iobfi b6 b5 b4 b 3 i n t e r r u p t g e n e r a t e c i r c u i t interrupt signal ibf, obe p8 2 /lad2 p 8 3 / l a d 3 p 8 1 / l a d 1 p8 0 /lad0 p 8 4 / l f r a m e input data bus buffer [3:0] output data bus buffer [7:4] output data bus buffer [3:0] p 8 6 / l c l k o u tp u t c o n t r o l c i r c u i t p 8 5 / l r e s e t 0 l p c d a t a b u s i n p u t d a t a c o m p a r a t o r t a r r e g i s t e r s y n c r e g i s t e r data bus buffer status register st a r t r e g i s t e r r d / w r r e g i s t e r a d d r e s s r e g i s t e r h h a d d r e s s r e g i s t e r h l a d d r e s s r e g i s t e r l h a d d r e s s r e g i s t e r l l i n t e r n a l c p u b u s b 2b 1b 0
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 48 fig. 44 interrupt request circuit of data bus buffer i n p u t b u f f e r f u l l f l a g 0 i b f 0 i n p u t b u f f e r f u l l f l a g 1 i b f 1 r i s i n g e d g e d e t e c t i o n c i r c u i t one-shot pulse generating circuit one-shot pulse generating circuit input buffer full interrupt request signal ibf o u t p u t b u f f e r f u l l f l a g 0 o b f 0 o u t p u t b u f f e r f u l l f l a g 1 o b f 1 o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t output buffer empty interrupt request signal obe i n t e r r u p t r e q u e s t i s s e t a t t h i s r i s i n g e d g e interrupt request is set at this rising edge ibf 0 ibf 1 ibf obf 0 ( obe 0) o b f 1 ( o b e 1 ) o b e o b e 0 o b e 1 r i s i n g e d g e d e t e c t i o n c i r c u i t r i s i n g e d g e d e t e c t i o n c i r c u i t r i s i n g e d g e d e t e c t i o n c i r c u i t
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 49 [lpc control register (lpccon)] 002a 16 sync output select bit (syncsel) 00 : ok 01 : long & ok 10 : err 11 : long & err lpc interface software reset bit (lpcsr) 0 : reset release (automatic) 1 : reset lpc interface enable bit (lpcben) 0 : p8 0 p8 6 works as port 1 : p8 0 p8 6 works as lpc interface data bus buffer 0 enable bit (dbben0) 0 : data bus buffer 0 disable 1 : data bus buffer 0 enable data bus buffer 1 enable bit (dbben1) 0 : data bus buffer 1 disable 1 : data bus buffer 1 enable bits 0 and 1 of the lpc control register (lpccon) specify the sync code output. bit 2 of the lpc control register (lpccon) enables the lpc inter- face to enter the reset state by software. when lpcsr is set to 1 , lpc interface is initialized in the same manner as the external l input to lreset pin (see figure 50). writing 0 to lpcsr the reset state will be released after 1.5 cycle of and this bit is cleared to 0 . [data bus buffer status register i (i = 0, 1) (dbbsts0, dbbsts1)] 0029 16 , 002c 16 bits 0, 1 and 3 are read-only bits and indicate the status of the data bus buffer. bits 2, 4, 5, 6 and 7 are user definable flags which can be read and written by software. the data bus buffer status register can be read out by the host controller when bit 2 of the slave address (a2) is 1 . ?it 0: output buffer full flag i (obfi) this bit is set to 1 when a data is written into the output data bus buffer i and cleared to 0 when the host controller reads out the data from the output data bus buffer i. ?it 1: input buffer full flag i (ibfi) this bit is set to 1 when a data is written into the input data bus buffer i by the host controller, and cleared to 0 when the data is read out from the input data bus buffer i by the internal cpu. ?it 3: xa2 flag (xa2i) the bit 2 of slave address is latched while a data is written into the input data bus buffer i. [input data bus buffer i(i=0,1) (dbbin0, dbbin1)] 0028 16 , 002b 16 in i/o write cycle from the host controller, the data byte of the data phase is latched to dbbini (i=0,1). the data of dbbini can be read out form the data bus buffer registers (dbb0, dbb1) address in sfr area. [output data bus buffer i (i = 0, 1) (dbbout0, dbbout1)] 0028 16 , 002b 16 writing data to data bus buffer registers (dbb0 , dbb1) address from the internal cpu means writing to dbbouti (i = 0, 1). the data of dbbouti (i = 1, 0) is read out from the host controller when bit 2 of slave address (a2) is 0 . [lpci address register h/l (lpc0adl, lpc1adl / lpc0adh, lpc1adh)] 0ff0 16 to 0ff3 16 the slave addresses of data bus buffer channel i(i=0,1) are defin- able by setting lpci address registers h/l (lpc0adl, lpc0adh, lpc1adl, lpc1adh ). these registers can be set and cleared any time. when the internal cpu reads lpci address register l, the bit 2 (a2) is fixed to 0 . the bit 2 of slave address (a2) is latched to xa2i flag when the host controller writes the data. the slave addresses, set in these registers, is used for comparing with the addresses from the host controller.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 50 fig. 46 data bus buffer control register fig. 45 lpc control register l p c c o n t r o l r e g i s t e r b i t n a m ef u n c t i o n b i t s y m b o l s y m b o la d d r e s sw h e n r e s e t l p c c o n0 0 2 a 1 6 0 0 0 0 0 0 0 0 2 0 : p 8 0 t o p 8 6 a s p o r t 1 : l p c i n t e r f a c e e n a b l e 0 : d a t a b u s b u f f e r 0 d i s a b l e 1 : d a t a b u s b u f f e r 0 e n a b l e l p c i n t e r f a c e e n a b l e b i t d a t a b u s b u f f e r 0 e n a b l e b i t d a t a b u s b u f f e r 1 e n a b l e b i t 0 : d a t a b u s b u f f e r 1 d i s a b l e 1 : d a t a b u s b u f f e r 1 e n a b l e c a n n o t w r i t e t o t h i s b i t . r e t u r n s 0 w h e n r e a d . l p c e n d b be n 0 d b be n 1 b 7b6b 5b 4b 3b 2b 1b 0 w r 0 0 : o k 0 1 : l o n g & o k 1 0 : e r r 1 1 : l o n g & e r r s y n c o u t p u t s e l e c t b i t s y n c s e l 0 : r e s e t r e l e a s e ( a u t o m a t i c ) 1 : r e s e t l p c i n t e r f a c e s o f t w a r e r e s e t b i t l p c s r d a t a b u s b u f f e r s t a t u s r e g i s t e r i ( i = 0 , 1 ) b i t n a m ef u n c t i o n b i t s y m b o l w r s y m b o la d d r e s sw h e n r e s e t d b b s t s 00 0 2 9 1 6 0 0 0 0 0 0 0 0 2 d b b s t s 10 0 2 c 1 6 0 0 0 0 0 0 0 0 2 o b f i o u t p u t b u f f e r f u l l f l a g 0 : b u f f e r e m p t y 1 : b u f f e r f u l l 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t h i s f l a g i n d i c a t e s t h e a 2 s t a t u s w h e n i b f i f l a g i s s e t . i n p u t b u f f e r f u l l f l a g user definable flag x a 2 i f l a g i b f i u 2 i x a 2 i b 7b 6b5b 4b 3b 2b 1b 0 u 4 i u 5 i u 6 i u 7 i user definable flag t h i s f l a g c a n b e f r e e l y d e f i n e d b y u s e r . t h i s f l a g c a n b e f r e e l y d e f i n e d b y u s e r .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 51 lpc i address register l ( i =0,1) (note2) symbol address when reset lpc0adl 0ff0 2 00000000 2 lpc1adl 0ff2 2 00000000 2 b 7b 6b 5b 4b 3b 2b 1b 0 l p c i a d d r e s s r e g i s t e r h ( i = 0 , 1 ) b 7b 6b 5b 4b 3b 2b 1b 0 notes 1: always returnes 0 when read , even if writing 1 to this bit. 2: do not set the same 16-bit slave address to both channel 0 and channel 1. s y m b o la d d r e s sw h e n r e s e t l p c 0 a d h 0 f f 1 2 0 0 0 0 0 0 0 0 2 l p c 1 a d h 0 f f 3 2 0 0 0 0 0 0 0 0 2 b i t n a m e b i t s y m b o l l p c s a d 0 s l a v e a d d r e s s b i t 0 s l a v e a d d r e s s b i t 1 s l a v e a d d r e s s b i t 2 (note 1) slave address bit 3 s l a v e a d d r e s s b i t 4 s l a v e a d d r e s s b i t 5 s l a v e a d d r e s s b i t 6 s l a v e a d d r e s s b i t 7 l p c s a d 1 l p c s a d 2 l p c s a d 3 l p c s a d 4 l p c s a d 5 l p c s a d 6 l p c s a d 7 w r l p c s a d 8 s l a v e a d d r e s s b i t 8 s l a v e a d d r e s s b i t 9 s l a v e a d d r e s s b i t 1 0 s l a v e a d d r e s s b i t 1 1 s l a v e a d d r e s s b i t 1 2 s l a v e a d d r e s s b i t 1 3 s l a v e a d d r e s s b i t 1 4 s l a v e a d d r e s s b i t 1 5 l p c s a d 9 l p c s a d 1 0 l p c s a d 1 1 l p c s a d 1 2 l p c s a d 1 3 l p c s a d 1 4 l p c s a d 1 5 w r b i t n a m e b i t s y m b o l fig. 47 lpc related registers
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 52 basic operation of lpc interface set up steps for lpc interface is as below. set the lpc interface enable bit (bit3 of lpccon) to 1 . choose which data bus buffer channel use. set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of lpccon) to 1 . set the slave address to lpci address register l and h (i = 0, 1) (lpc0adl, lpc0adh, lpc1adl, lpc1adh). (1) example of i/o write cycle the i/o write cycle timing is shown in figure 48. the standard transfer cycle number of i/o write cycle is 13. the communication starts from the falling edge of lframe. the data on lad [3:0] is monitored at every rising edge of lclk. 1 st clock: the last clock when lframe is low . the host send 0000 2 on lad [3:0] for communication start. 2 nd clock: lframe is high . the host send 001x 2 on lad [3:0] to inform the cycle type as i/o write. from 3 rd clock to 6 th clock : in these four cycles , the host sends 16-bit slave address. the 3885 compares it with the lpci ad- dress register h and l (i = 0, 1). 3 rd clock: the slave address bit [15:12]. 4 th clock: the slave address bit [11:8]. 5 th clock: the slave address bit [7:4]. 6 th clock: the slave address bit [3:0]. 7 th clock and 8 th clock are used for one data byte transfer. the data is written to the input data bus buffer (dbbini, i = 0, 1) 7 th clock: the host sends the data bit [3:0]. 8 th clock: the host sends the data bit [7:4]. 9 th clock and 10 th clock are for turning the communication direc- tion from the host the peripheral to the slave the host. 9 th clock: the host outputs 1111 2 on lad [3:0]. 10 th clock: the lad [3:0] is set to tri-state by the host to turn the communication direction. 11 th clock: the 3885 outputs 0000 2 (sync ok) to lad [3:0] for acknowledgment. 12 th clock: the 3885 outputs 1111 2 to lad [3:0]. in this timing the address bit 2 is latched to xa2i (bit3 of dbbstsi), ibfi (bit 1 of dbbstsi) is set to 1 and ibf interrupt signal is generated. 13 th clock: the lad [3:0] is set to tri-state by the host to turn the communication direction. (2) example for i/o read cycle the i/o read cycle timing is shown in figure 49. the standard transfer cycle number of i/o read cycle is 13. the data on lad [3:0] is monitored at every rising edge of lclk. the communica- tion starts from the falling edge of lframe. 1 st clock: the last clock when lframe is low . the host sends 0000 2 on lad [3:0] for communication start. 2 nd clock: lframe is high . the host sends 000x 2 on lad [3:0] to inform the cycle type as i/o read. from 3 rd clock to 6th clock: in these four cycles , the host sends 16-bit slave address. the 3885 compares it with the lpci ad- dress register h or l (i = 0, 1). 3 rd clock: the slave address bit [15:12]. 4 th clock: the slave address bit [11:8]. 5 th clock: the slave address bit [7:4]. 6 th clock: the slave address bit [3:0]. 7 th clock and 8 th clock are used for turning the communication di- rection from the host the peripheral to the peripheral the host. 7 th clock: the host outputs 1111 2 on lad [3:0]. 8 th clock: the lad [3:0] is set to tri-state by the host to turn the communication direction. 9 th clock: the 3885 outputs 0000 2 (sync ok) to lad [3:0] for acknowledgment. 10 th clock and 11 th clock are used for one data byte transfer from the output data bus buffer i (dbbouti) or data bus buffer status register i (dbbstsi). 10 th clock: the 3885 sends the data bit [3:0]. 11 th clock: the 3885 sends the data bit [7:4]. 12 th clock: the 3885 outputs 1111 2 to lad [3:0]. in this timing obfi (bit 2 of dbbstsi) is cleared to 0 and obe interrupt signal is generated. 13 th clock: the lad [3:0] is set to tri-state by the host to turn the communication direction.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 53 fig. 48 data and command write timing d a t a w r i t e ( i / o w r i t e c y c l e ) l c l k l f r a m e l a d [ 3 : 0 ] i n p u t d a t a b u s b u f f e r i x a 2 i f l a g ibfi flag command write (i/o write cycle) l c l k l f r a m e lad [3:0] s t a r t cyctype + dir a d d r e s s data tar sync t a r start cyctype + dir tarsynctar driven by the host driven by the 3885 (note) (note) address data i n p u t d a t a b u s b u f f e r i x a 2 i f l a g i b f i f l a g driven by the host d r i v e n b y t h e 3 8 8 5 n o t e : l a d 0 t o l a d 3 p i n s r e m a i n t r i - s t a t e a f t e r t r a n s f e r c o m p l e t i o n .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 54 data read (i/o read cycle) l c l k l f r a m e l a d [ 3 : 0 ] o u t p u t d a t a b u s b u f f e r i o b f i f l a g s t a r t c y c t y p e + d i r a d d r e s st a rsyncd a t at a r status read (i/o read cycle) l c l k l f r a m e l a d [ 3 : 0 ] obfi flag start c y c t y p e + d i r address tar sync data tar driven by the host driven by the 3885 ( n o t e 1 ) ( n o t e 1 ) (note 2) driven by the host driven by the the 3885 notes 1: lad 0 to lad 3 pins remain tri-state after transfer completion. 2: obfi flag does not change. fig. 49 data and status read timing
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 55 fig. 50 reset timing and block lreset l p c i n t e r f a c e r e s e t s i g n a l c p u d a t a b u s b i t 2 lpcsr write signal c p u r e s e t r c p u r e s e t r table 17 reset conditions of lpc interface function pin name / internal register p8 0 /lad 0 p8 1 /lad 1 p8 2 /lad 2 p8 3 /lad 3 p8 4 /lframe p8 5 /lreset p8 6 /lclk input data bus buffer registeri output data bus buffer registeri uxi flag 7, 6, 5, 4, 2 xa 2i flag ibfi flag obfi flag lpci address register lpccon lreset = l tri-state input lpc bus interface function input keep same value before lreset goes l . initialization to 0 . initialization to 0 . initialization to 0 . keep same value before lreset goes l . note there is possibility to generate ibf interrupt request. there is possibility to generate obe interrupt request. pin internal register
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 56 serialized interrupt the serialized irq circuit communicates the interrupt status to the host controller based on the serialized irq support for pci system, version 6.0. table 18 shows the summary of serialized interrupt of 3885. item the factors of serialized irq the number of frame operation clock clock restart clock stop inhibition function the numbers of serialized irq factor that can output simultaneously are 3. ?channel 0 (irq1,irq2) ? setting software irqi (i = 1, 12) request bit (bits 0, 1 of serirq) to ?. ? the ??of obf0 and hardware irqi ( i=1, 12) request bit (bits 3, 4 of sercon) to ?. ?channel 1 (irqx ; user selectable) ? setting the irqx request bit (bit 7 of serirq) to 1. ? the ??of obf1 and hardware irqx request bit to 1. ?channel 0 (irq1, irq12) ? setting software irq1 request bit (bit 0 of serirq) to ??or detecting ??of obf0 with 1 of hardware irq1 request bit (bit 4 of sercon) selects irq1 frame . ? setting irq12 software request bit (bit 1 of serirq) to ??or detecting ??of obf0 with ??of hardware irq1 request bit (bit 4 of sercon) selects irq12 frame. ?channel 1 (irqx ; user selectable) setting irqx frame select bit (bit 2-6 of serirq) selects irq 1?5 frame or extend frame 0?0. synchronized with lclk (max. 33 mhz). lpc clock restart enable bit (bit 1 of sercon) enables restart owing to ??output of clkrun with the interrupt when the lpc clock has stopped or slowed down. lpc clock stop inhibition bit (bit 2 of sercon) enables the inhibition of clock stop control during the irqser cycle when the clock tends to stop or slow down. table 18 smmary of serialized irq function
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 57 fig. 51 block diagram of serialized interrupt clock monitor control circui t s e r i a l i z e d i n t e r r u p t r e q u e s t c o n t r o l c i r c u i t internal data bus s e r i a l i z e d i r q c o n t r o l r e g i s t e r s e r i a l i z e d i r q r e q u e s t r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 l c l k serialized irq request f r a m e n u m b e r serialized interrupt control circuit i r q x f r a m e n u m b e r o b f i n t e r r u p t c o n t r o l c l o c k s t o p i n h i b i t i o n e n a b l e a n d c l o c k r e s t a r t e n a b l e o b f 0 o b f 1 clock operation status and finish acknowledgement clock restart request and start frame activate request c l k r u n # serirq l r e s e t # c p u c l o c k s o f t w a r e s e r i a l i z e d i r q r e q u e s t b 7 b 6b 5b 4b 3b2b1b0 s e r i a l i z e d i r q e n a b l e * open drain *
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 58 fig. 52 configuration of serialized irq control register register explanation the serialized irq function is configured and controlled by the se- rialized irq request register (serirq) and the serialized irq control register (sercon). [serialized irq control register (sercon)] 001d 16 bit 0 : serialized irq enable bit (sirqen ) this bit enables/disables the serialized irq interface. when this bit is 1 , use of serialized irq is enabled. then p8 7 functions as irq/data line (serirq) and p4 7 functions as clkrun. output structure of clkrun pin becomes n-channel open drain. bit 1 : lpc clock restart enable bit (runen ) setting this bit to 1 enables clock restart with l output of clkrun. bit 2 : lpc clock stop inhibition bit (supen ) setting this bit to 1 makes clkrun output change to l for in- hibiting the clock stop. bit 3 : hardware irq1 request bit (seir1) when this bit is 1 , obf 0 status is directly connected to the irq 1 frame. bit 4 : hardware irq12 request bit (seir12 ) when this bit is 1 , obf 0 status is directly connected to irq12 frame. bit 5 : hardware irqx request bit (seirx ) when this bit is 1 , obf 1 status is directly connected to the irq x frame. bit 6 : irq1/irq12 disable bit (sch0en ) this bit controls whether the serialized irq channel 0 transfers the irq1 and irq12 frame to the host or not. bit 7 : irqx output polarity bit (sch1pol) this bit selects irx frame output level. serialized irq control registe r bit name function bit symbol w r symbol address when reset sercon 001d 16 00000000 2 s i r q e n serialized irq enable bit 0 : serialized irq disable 1 : serialized irq enable 0 : clock restart disable 1 : clock restart enable 0 : s t o p i n h i b i t i o n c o n t r o l d i s a b l e 1 : s t o p i n h i b i t i o n c o n t r o l e n a b l e 0 : no irq1 request 1 : obf 0 synchronized irq1 request l p c c l o c k r e s t a r t e n a b l e b i t lpc clock stop inhibition bit hardware irq1 request bit runen s u p e n s e i r 1 b 7b 6b 5b 4b 3b 2b 1b 0 h a r d w a r e i r q 1 2 r e q u e s t b i t 0 : no irq12 request 1 : obf 0 synchronized irq12 request seirx hardware irqx request bit 0 : n o i r q x r e q u e s t 1 : o b f 1 s y n c h r o n i z e d i r q x r e q u e s t s e i r 1 2 sch0en i r q 1 / i r q 1 2 d i s a b l e b i t 0 : i r q 1 / i r q 1 2 o u t p u t e n a b l e 1 : i r q 1 / i r q 1 2 o u t p u t d i s a b l e i r q x o u t p u t p o l a r i t y b i t0 : - r e q u e s t h i z - h i z - h i z - n o r e q u e s t l - h - h i z 1 : - r e q u e s t l - h - h i z - n o r e q u e s t h i z - h i z - h i z s c h 1 p o l
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 59 fig. 53 structure of serialized irq request register [serialized irq request register (serirq)] 001f 16 the interrupt source is definable by this register. bit 0 : software irq1 request bit (ir1) serirq line shows ir1 value at the sample phase of irq1 frame, when the sch0en is 1 . bit 1 : software irq12 request bit (ir12) serirq line shows ir12 value at the sample phase of irq12 frame, when the sch0en is 1 . bits 2-6 : irqx frame select bits (isi, i = 0?) these bits select the active irq frame of serial irq channel 1. when these bit are 00000 2 , the serial irq channel 1 is disabled. bit 7 : software irqx request bit (irx) serirq line shows irx value at the sample phase of irqx frame which is selected by bits 2 to 6 of serirq. output level is select- able by the irqx output polarity bit (sch1pol). serialized irq request register w h e n r e s e t 0 0 0 0 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b7 b6 b5 b4 b3 b2 b1 b0 irqx frame select bit s o f t w a r e i r q x r e q u e s t b i t 0: no irqx request 1: irqx request b6b5b4b3b2 0 0 0 0 0 : disable serial irq channel 1 0 0 0 0 1 : irq1 frame 0 0 0 1 0 : irq2 frame 0 0 0 1 1 : irq3 frame 0 0 1 0 0 : irq4 frame 0 0 1 0 1 : irq5 frame 0 0 1 1 0 : irq6 frame 0 0 1 1 1 : irq7 frame 0 1 0 0 0 : irq8 frame 0 1 0 0 1 : irq9 frame 0 1 0 1 0 : irq10 frame 0 1 0 1 1 : irq11 frame 0 1 1 0 0 : irq12 frame 0 1 1 0 1 : irq13 frame 0 1 1 1 0 : irq14 frame 0 1 1 1 1 : irq15 frame 1 0 0 0 0 : do not select 1 0 0 0 1 : do not select 1 0 0 1 0 : do not select 1 0 0 1 1 : do not select 1 0 1 0 0 : do not select 1 0 1 0 1 : extend frame 0 1 0 1 1 0 : extend frame 1 1 0 1 1 1 : extend frame 2 1 1 0 0 0 : extend frame 3 1 1 0 0 1 : extend frame 4 1 1 0 1 0 : extend frame 5 1 1 0 1 1 : extend frame 6 1 1 1 0 0 : extend frame 7 1 1 1 0 1 : extend frame 8 1 1 1 1 0 : extend frame 9 1 1 1 1 1 : extend frame 10 0 : n o i r q 1 r e q u e s t 1 : i r q 1 r e q u e s t 0: no irq12 request 1: irq12 request s o f t w a r e i r q 1 r e q u e s t b i t software irq12 request bit ir1 ir12 is0 is1 is2 is3 is4 irx symbol serirq a d d r e s s 0 0 1 f 1 6
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 60 operation of serialized irq a cycle operation of serialized irq starts with start frame and fin- ishes with stop frame. there are two modes of operation : continuous (idle) mode and quiet (active) mode. the next opera- tion mode is determined by monitoring the stop frame pulse width. timing of serialized irq cycle figure 54 shows the timing diagram of serialized irq cycle. (1) start frame the start frame is detected when the serirq line remains l in 4 to 8 clocks. fig. 54 timing diagram of serialized irq cycle (2) irq/data frame each irq/data frame is three clocks. when the irqi (i = 0, 1, x) request is 0 , then the serirq line is driven to l during the sample phase (1 st clock) of the corresponding irq/data frame, to h during the recovery phase (2 nd clock), to tri-state during the turn-around phase (3 rd clock). when the irqi request is 1 , then the serirq line is tri-state in all phases (3 clocks period). (3) stop frame the stop frame is detected when the serirq line remains l in 2 or 3 clocks. the next operation mode is quiet mode when the pulse width of l is 2 clocks. the next operation mode is the continuous mode when the pulse width is 3 clocks. start frame i r q 0 f r a m e irq1 frame irq15 frame iochk frame irq1 device control s t o p f r a m e to t h e n e x t c y c l e irq15 device control host control c l o c k s e r i r q driver source h o s t c o n t r o l
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 61 operation mode figure 55 shows the timing of continuous mode; figure 56 shows that of quiet mode. (1) continuous mode serialized irq cycles starts in continuous mode after cpu reset in the case of lreset = ??and the previous stop frame being 3 clocks. fig. 55 timing diagram of continuous mode fig. 56 timing diagram of quiet mode (2) quiet mode at clock stop, clock slow down or the pulse width of the last stop frame being 2 clocks, it is the quiet mode. in this mode the 3885 drives the serirq line to ??in the 1 st clock. after that the host drives the rest start frame (note). the irq1 frame, irq12 frame or irqx frame is asserted. after receiving the start frame; the irq1 frame, irq12 frame or irqx frame is asserted. note : if the pulse width of ??is less than 4 clocks, or 9 clocks or more; the start frame is not detected and the next start (the falling edge of serirq) is waited. note: when the sum of pulse width of ??driven by the 3885 in the 1 st clock and driven by the host in the rest clocks is within 4 to 8-clock cycles, the start frame is detected. if the sum of pulse width of ??is less than 4 clocks, or 9 clocks or more; the start frame is not detected and the next start (the falling edge of serirq) is waited. s t a r t f r a m e ( n o t e ) i r q0 f r a m e i r q 1 f r a m e ho s t 3 8 8 5 l c l k s e r i r q l i n e dr i v e s o u r c e i r q 2 f r a m e i r q 3 f r a m e ho s ts e r i r q o u t p u t 3 8 8 5s e r i r q o u t p u t n o t e : t h e s t a r t f r a m e c o u n t i s 4 c l o c k s a s e x e m p l e . s t a r t f r a m e ( n o t e ) i r q 0 f r a m e i r q 1 f r a m e ho s t 3 8 8 5 l c l k s e r i r q l i n e dr i v e s o u r c e i r q 2 f r a m e i r q 3 f r a ho s t s e r i r q o u t p u t 3 8 8 5s e r i r q o u t p u t 3 8 8 5 n o t e : t h e s t a r t f r a m e c o u n t i s 4 c l o c k s a s e x e m p l e
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 62 clock restart/stop inhibition request asserting the clkrun signal can request the host to restart for clocks stopped or slowed down, or maintain the clock tending to stop or slow down. figure 57 shows the timing diagram of clock restart request; fig- ure 58 shows an example of timing of clock stop inhibition request. fig. 57 timing diagram of clock restart request fig. 58 timing diagram of clock stop inhibition request (2) clock stop inhibition request in case the lpc clock stop inhibition bit (bit 2 of sercon) is ? and the serialized interrupt request is held, if the lclk tends to stop, the 3885 drives clkrun to ??for requesting the pci clock generator not to stop lclk. (1) clock restart operation in case the lpc clock restart enable bit (bit 1 of sercon) is ? and the clkrun (bus) is ?? when the serialized interrupt re- quest occurs, the 3885 drives clkrun to ??for requesting the pci clock generator to restart the lclk if the clock is slowed down or stopped. l c l k bus clkrun c e n t r a l r e s o u r c e c l k r u n 3 8 8 5 c l k r u n b u s s e r i r q ho s t s e r i r q 3885 serirq interrupt request internal restart request signal start fram e r e s t a r t f r a m e l c l k b u s c l k r u n c e n t r a l r e s o u r c e c l k r u n 3885 clkrun i n t e r r u p t r e q u e s t internal inhibition request signal bus serirq irqser cycle inhibition request
63 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter [a-d conversion register 1,2 (ad1, ad2)] 0035 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 is the conversion mode se- lection bit. when this bit is set to ?,?the a-d converter becomes the 10-bit a-d mode. when this bit is set to ?,?that becomes the 8-bit a-d mode. the conversion result of the 8-bit a-d mode is stored in the a-d conversion register 1. as for 10-bit a-d mode, 10-bit reading or 8-bit reading can be performed by selecting the reading procedure of the a-d conversion register 1, 2 after a-d conversion is completed (in figure 60). the a-d conversion register 1 performs the 8-bit reading inclined to msb after reset, the a-d conversion is started, or reading of the a-d converter register 1 is generated; and the register becomes the 8-bit reading inclined to lsb after the a-d converter register 2 is generated. [ad/da control register (adcon)] 0034 16 the ad/da control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 3 signals the completion of an a-d conversion. the value of this bit remains at ??during an a-d conversion, and changes to ??when an a-d conversion ends. writing ??to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024, and outputs the divided voltages in the 10-bit a-d mode (256 division in 8-bit a-d mode). the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref (see below), with the input voltage. 10-bit a-d mode (10-bit reading) v ref = ? n (n = 0?023) 10-bit a-d mode (8-bit reading) v ref = ? n (n = 0?55) 8-bit a-d mode v ref = ? (n?.5) (n = 1?55) =0 (n = 0) fig. 59 structure of ad/da control register channel selector the channel selector selects one of ports p6 0 /an 0 to p6 7 /an 7 , and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to ?? note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. v ref 256 v ref 256 fig. 60 structure of 10-bit a-d mode reading v ref 1024 a d / d a c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 6 0 / a n 0 0 0 1 : p 6 1 / a n 1 0 1 0 : p 6 2 / a n 2 0 1 1 : p 6 3 / a n 3 1 0 0 : p 6 4 / a n 4 1 0 1 : p 6 5 / a n 5 1 1 0 : p 6 6 / a n 6 1 1 1 : p 6 7 / a n 7 a - d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d p w m 0 o u t p u t p i n s e l e c t i o n b i t 0 : p 5 6 / p w m 0 1 1 : p 3 0 / p w m 0 0 p w m 1 o u t p u t p i n s e l e c t i o n b i t 0 : p 5 7 / p w m 1 1 1 : p 3 1 / p w m 1 0 d a 1 o u t p u t e n a b l e b i t 0 : d a 1 o u t p u t d i s a b l e d 1 : d a 1 o u t p u t e n a b l e d d a 2 o u t p u t e n a b l e b i t 0 : d a 2 o u t p u t d i s a b l e d 1 : d a 2 o u t p u t e n a b l e d b 7 b 0 b 2 b 1 b 0 1 0 - b i t r e a d i n g ( r e a d a d d r e s s 0 0 3 8 1 6 b e f o r e 0 0 3 5 1 6 ) ( a d d r e s s 0 0 3 8 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) 8 - b i t r e a d i n g ( r e a d o n l y a d d r e s s 0 0 3 5 1 6 ) ( a d d r e s s 0 0 3 5 1 6 ) b 8 b 7b 6b 5b 4 b 3b 2b 1b 0 b 7 b 0 b 9 b 7 b 0 n o t e : b i t s 2 t o 6 o f a d d r e s s 0 0 3 8 1 6 b e c o m e s 0 a t r e a d i n g . b 9b 8b 7b 6 b 5b 4b 3 b 2 b 7 b 0 0
64 3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 61 block diagram of a-d converter channel selector a-d control circuit a-d conversion register 1 resistor ladder v ref av ss comparator a-d interrupt request b7 b0 3 10 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 data bus ad/da control register (address 0034 16 ) a-d conversion register 2 (address 0038 16 ) (address 0035 16 )
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 65 d-a converter the 3885 group has two internal d-a converters (da 1 and da 2 ) with 8-bit resolution. the d-a converter is performed by setting the value in each d-a conversion register. the result of d-a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to ?? when using the d-a converter, the corresponding port direction register bit (p5 6 for da 1 or p5 7 for da 2 ) must be set to ??(input status). the output analog voltage v is determined by the value n (decimal notation) in the d-a conversion register as follows: v = v ref ? n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to ?0 16 ? the da output enable bits are cleared to ?? and the p5 6 /da 1 /pwm 01 and p5 7 /da 2 /pwm 11 pins become high impedance. the da output does not have buffers. accordingly, connect an ex- ternal buffer when driving a low-impedance load. fig. 62 block diagram of d-a converter fig. 63 equivalent connection circuit of d-a converter (da1) p 5 6 / d a 1 / p w m 0 1 d - a 1 c o n v e r s i o n r e g i s t e r ( 8 ) r - 2 r r e s i s t o r l a d d e r d a 1 o u t p u t e n a b l e b i t p 5 7 / d a 2 / p w m 1 1 d - a 2 c o n v e r s i o n r e g i s t e r ( 8 ) r-2r resistor ladder d a 2 o u t p u t e n a b l e b i t d a t a b u s av ss v r e f 0 1 m s b 0 1 r 2r r 2r r 2r r 2r r 2 r r 2 r r 2r 2 r l s b 2 r p 5 6 / d a 1 / p w m 0 1 d-a1 conversion register d a 1 o u t p u t e n a b l e b i t
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 66 comparator circuit comparator configuration the comparator circuit consists of the ladder resistors, the analog comparators, a comparator control circuit, the comparator refer- ence input selection bit (bit 7 of pctl2), a comparator data register (cmpd), the comparator reference power source input pin (p2 0 /cmp ref ) and analog input pins (p3 0 p3 7 ). the analog input pin (p3 0 p3 7 ) also functions as an ordinary digital port. comparator operation to activate the comparator circuit, first set port p3 to input mode by setting the corresponding direction register (p3d) to 0 to use port p3 as an analog voltage input pin. the internal fixed analog voltage (v cc ? 29/32) can be generated by setting 1 to the com- parator reference input selection bit (bit 7 of pctl2). the internal fixed analog voltage becomes about 2.99 v at v cc = 3.3 v. when setting 0 to the comparator reference input selection bit, the p2 0 / cmp ref pin becomes the comparator reference power source in- put pin and it is possible to input the comparator reference power source optionally from the external. the voltage comparison is im- mediately performed by the writing operation to the comparator data register (cmpd). after 14 cycles of the internal system clock (the time required for the comparison), the comparison result is stored in the comparator data register (cmpd). if the analog input voltage is greater than the internal reference voltage, each bit of this register is 1 ; if it is less than the internal reference voltage, each bit of this register is 0 . to perform an- other comparison, the voltage comparison must be performed again by writing to the comparator data register (cmpd). read the result when 14 cycles of or more have passed after the comparator operation starts. the ladder resistor is turned on dur- ing 14 cycles of , which is required for the comparison, and the reference voltage is generated. an unnecessary current is not consumed because the ladder resistor is turned off while the com- parator operation is not performed. since the comparator consists of capacitor coupling, the electric charge may lost if the clock fre- quency is low. keep the clock frequency more than 1 mhz during the comparator operation. do not execute the stp, wit, or port p3 i/o instruction. fig. 64 comparator circuit v ss 8 8 v cc p3 (8) p3 7 p3 6 p3 0 b0 comparator reference input selection bit (bit 7 of pctl2) comparator data register compar- ator ladder resistor connecting signal comparator control circuit comparator connecting signal compar- ator compar- ator p2 0 /cmp ref v cc ? 29/32 1 0 data bus
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 67 reset circuit ____________ to reset the microcomputer, reset pin should be held at an l level for 16 x in cycle or more. (when the power source voltage should be between 3.3v 0.3v and the oscillation should be ____________ stable.) then the reset pin set to h , the reset state is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.6 v for v cc of 3.0 v. fig. 66 reset sequence fig. 65 reset circuit example reset internal reset data address sync x in : 10.5 to 18.5 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( ) is f(x in )=8 f( ). 2: the question marks (?) indicate an undefined data that depends on the previous state. reset address from the vector table . notes (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=3.0 v
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 68 fig. 67 internal status at reset port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) serialized irq control register (sercon) watchdog timer control register (wdtcon) serialized irq request register (serirq) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) data bus buffer register 0 (dbb0) data bus buffer status register 0 (dbbsts0) lpc control register (lpccon) data bus buffer register 1 (dbb1) data bus buffer status register 1 (dbbsts1) comparator data register (cmpd) port control register 1 (pctl1) port control register 2 (pctl2) pwm0h register (pwm0h) pwm0l register (pwm0l) pwm1h register (pwm1h) pwm1l register (pwm1l) ad/da control register (adcon) a-d conversion register 1 (ad1) d-a1 conversion register (da1) d-a2 conversion register (da2) a-d conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) lpc0 address register l (lpc0adl) lpc0 address register h (lpc0adh) lpc1 address register l (lpc1adl) lpc1 address register h (lpc1adh) port p5 input register (p5i) port control register 3 (pctl3) flash memory control register (fmcr) processor status register program counter (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) (69) (70) (71) (72) (73) register contents 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff8 16 0ff9 16 0ffe 16 (ps) (pc h ) (pc l ) address ff 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 address register contents 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 ff 16 00 16 ff 16 xxxxxxxx 0001000x xxxxxxxx xxxxxxxx xxxxxxxx 00011010 10000000 11100000 00111111 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000000xx fffd 16 contents fffc 16 contents 01 001000 1 xx xx xx x note : x : not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. xxxxxxxx x0 xxxxxx x0xxxxxx 00 001000 0 xx x 1 0 00
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 69 clock generating circuit the 3885 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer s recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately af- ter power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set sufficient time for oscillation to stabilize. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1 , set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source, and the output of the prescaler 12 is connected to timer 1. set the timer 1 interrupt enable bit to disabled ( 0 ) before executing the stp instruction. oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the cpu (remains at h ) until timer 1 underflows. the internal clock is supplied for the first time, when timer 1 underflows. therefore make sure not to set the timer 1 interrupt request bit to 1 before the stp instruction stops the oscillator. when the oscillator is re- started by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 68 ceramic resonator circuit fig. 69 external clock input circuit v cc v ss x cin x cout x in x out open open external oscillation circuit external oscillation circuit v cc v ss x cin x cout x in x out c in c out c cin c cout rf rd
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 70 fig. 70 system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction t i m i n g ( i n t e r n a l c l o c k ) s r q s t p i n s t r u c t i o n s r q m a i n c l o c k s t o p b i t s r q 1 / 2 1 / 4 x in x out x c o u t x cin i n t e r r u p t r e q u e s t r e s e t i n t e r r u p t d i s a b l e f l a g l 1/2 p o r t x c s w i t c h b i t 1 0 l o w - s p e e d m o d e h i g h - s p e e d o r m i d d l e - s p e e d m o d e middle-speed mode h i g h - s p e e d o r l o w - s p e e d m o d e m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e 1 ) n o t e s 1 : e i t h e r h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e c p u m o d e r e g i s t e r . w h e n l o w - s p e e d m o d e i s s e l e c t e d , s e t p o r t x c s w i t c h b i t ( b 4 ) t o 1 . 2 : f ( x i n ) / 1 6 i s s u p p l i e d a s t h e c o u n t s o u r c e t o t h e p r e s c a l e r 1 2 a t r e s e t . w h e n e x c i t i n g s t p i n s t r u c t i o n , t h e c o u n t s o u r c e d o e s n o t c h a n g e e i t h e r f ( x i n ) ) / 1 6 o r f ( x c i n ) ) / 1 6 a f t e r r e l e a s i n g s t o p m o d e . o s c i l l a t i o n s t a b i l i z i n g t i m e i s n o t f i x e d 0 1 f f 1 6 w h e n t h e b i t 6 o f p c t l 2 i s 1 . m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e 1 ) f f 1 6 0 1 1 6 p r e s c a l e r 1 2 t i m e r 1 r e s e t o r s t p i n s t r u c t i o n ( n o t e 2 )
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 71 fig. 71 state transitions of system clock c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o p e r a t i n g 1 : s t o p p e d c m 7 , c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t b 7 b 6 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e n o t e s rese t c m 4 1 0 c m 4 0 1 c m 6 1 0 c m 4 1 0 c m 6 1 0 c m 7 1 0 c m 4 1 0 c m 5 1 0 c m 6 1 0 c m 6 1 0 cpu mode register b7 b 4 c m 7 0 1 c m 6 1 0 (cpum : address 003b 16 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) middle-speed mode (f( )=1 mhz) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) cm 7 =1 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) c m 7 = 1 c m 6 = 0 c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) low-speed mode (f( )=16 khz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y c o n n e c t i n g p r e s c a l e r 1 2 a n d t i m e r 1 i n m i d d l e / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s b y t i m e r 1 a n d t i m e r 2 i n l o w - s p e e d m o d e . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k .
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 72 flash memory mode the 3885 (flash memory version) has an internal new dinor flash memory that can be reprogrammed with 2 power sources when v cc is 3.3 v. for this flash memory , two flash memory modes are available in which to read, program, and erase: parallel i/o and a cpu repro- gram mode in which the flash memory can be manipulated by the central processing unit (cpu). each mode is detailed in the pages to follow. fig. 72 block diagram of flash memory version the flash memory of the 3885 is divided into user rom area and boot rom area as shown in figure 72. in addition to the ordinary user rom area to store a microcom- puter operation control program, 3885 program has a boot rom area that is used to store a program to control reprogramming in cpu reprogram mode. the user can store a reprogram control software in this area that suits the users application system. this boot rom area can be reprogrammed in only parallel i/o mode. 8000 16 block 0 : 32kbyte user rom area 4 kbyte f000 16 ffff 16 ffff 16 boot rom area notes 1: the boot rom area can be rewritten in only parallel input/ output mode. 2: to specify a block, use the maximum address in the block. product name flash memory start address m38859ff 1000 16 parallel i/o mode 8000 16 block 0 : 32 kbyte ffff 16 cpu reprogram mode user rom area 4 kbyte f000 16 ffff 16 boot rom area bsel = 0 bsel = 1 user area / boot area selection bit = 0 user area / boot area selection bit = 1 block 1 : 28 kbyte 1000 16 1000 16 block 1 : 28 kbyte
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 73 bus operation modes read _____ _____ the read mode is entered by pulling the oe pin low when the ce _____ _____ pin is low and the we and rp pins are high. there are two read modes: array, and status register, which are selected by software command input. in read mode, the data corresponding to each soft- ware command entered is output from the data i/o pins d 0 d 7 . the read array mode is automatically selected when the device is pow- ered on or after it exits deep power down mode. output disable _____ the output disable mode is entered by pulling the ce pin low and the _____ _____ _____ we, oe, and rp pins high. also, the data i/o pins are placed in the high-impedance state. standby _____ _____ the standby mode is entered by driving the ce pin high when the rp pin is high. also, the data i/o pins are placed in the high-impedance _____ state. however, if the ce pin is set high during erase or program operation, the internal control circuit does not halt immediately and normal power consumption is required until the operation under way is completed. write _____ _____ the write mode is entered by pulling the we pin low when the ce pin _____ _____ is low and the oe and rp pins are high. in this mode, the device accepts the software commands or write data entered from the data i/o pins. a program, erase, or some other operation is initiated de- pending on the content of the software command entered here. the input data such as address and software command is latched at the _____ _____ rising edge of we or ce whichever occurs earlier. deep power down _____ the deep power down is entered by pulling the rp pin low. also, the data i/o pins are placed in the high-impedance state. when the de- vice is freed from deep power down mode, the read array mode is selected and the content of the status register is set to 80 16 . if the _____ rp pin is pulled low during erase or program operation, the opera- tion under way is canceled and the data in the relevant block be- comes invalid. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in fig- ure 72 can be rewritten. the bsel pin is used to choose between these two areas. the user rom area is selected by pulling the bsel input low; the boot rom area is selected by driving the bsel input high. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 72. the user rom area is 60 kbytes in size. in parallel i/o mode, it is located at addresses 1000 16 through ffff 16 . the boot rom area is 4 kbytes in size. in parallel i/o mode, it is located at addresses f000 16 through ffff 16 . make sure program and block erase opera- tions are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. functional outline (parallel i/o mode) in parallel i/o mode, bus operation modes read, output disable, standby, write, and deep power down are selected by the status _____ _____ _____ _____ of the ce, oe, we, and rp input pins. the contents of erase, program, and other operations are selected by writing a software command. the data, status register, etc. in memory can only be read out by a read after software command input. program and erase operations are controlled using software com- mands. the following explains about bus operation modes, software com- mands, and status register. d 0 to d 7 data output status register data output hi-z hi-z command/data input command input command input hi-z _____ rp v ih v ih v ih v ih v ih v ih v ih v il ______ we v ih v ih v ih x v il v il v il x _____ oe v il v il v ih x v ih v ih v ih x _____ ce v il v il v il v ih v il v il v il x pin name mode array status register output disabled stand by program write erase other deep power down read note : x can be v il or v ih . table 19 relationship between control signals and bus operation modes parallel i/o mode the parallel i/o mode is entered by making connections shown in figures 73 and then turning the vcc power supply on. address the user rom is divided into two blocks as shown in figure 72. the block address referred to in this data sheet is the maximum address value of each block.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 74 table 20 description of pin function (flash memory parallel i/o mode) pin name signal name i/o function v cc ,v ss power supply input apply 3.0 0.3 v to the vcc pin and 0 v to the vss pin. cnv ss power suppy input connect to v pp = 5v 0.5v. i reset input input l level. i reset i x in clock input connect a ceramic or crystal resonator between the x in and x out pins. when entering an externally derived clock, enter it from x in and leave x out open. i x out clock output o av ss analog power supply input v ref reference voltage input i connect to vss. connect to vss. p0 0 to p0 7 data i/o d 0 to d 7 these are data d 0 d 7 input/output pins. i/o p1 0 to p1 7 i these are address a 8 a 15 input pins. address input a 0 to a 7 this is address a 0 a 7 input pins. i p2 0 to p2 7 i p3 0 input p3 0 input h or l or keep open. address input a 8 to a 15 p3 3 i p3 4 i we input rp input this is a rp input pin. this is a we input pin. i p3 7 i p3 6 p4 7 input p4 7 i ce input oe input this is a oe input pin. this is a ce input pin. p3 5 o ry/by output this is a ry/by output pin. p5 0 to p5 7 input p5 i p4 0 to p4 5 input p4 0 to p4 5 i i i p3 1 bsel input this is a bsel input pin. i p3 2 input p3 2 input h or l or keep open. p4 6 flash mode input connect l for pallarel i/o mode. i input h or l or keep open. p6 0 to p6 7 input p6 i p7 0 to p7 7 input p7 i p8 0 to p8 7 input p8 i input h or l or keep open. input h or l or keep open. input h or l or keep open. input h or l or keep open. input h or l or keep open.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 75 fig. 73 pin connection diagram in parallel i/o mode 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 /pwm 00 p3 1 /pwm 10 p6 2 /an 2 p6 1 /an 1 p4 4 /r x d p4 3 /int 1 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 av ss p6 7 /an 7 v ref v cc p8 0 /lad 0 p8 1 /lad 1 p8 2 /lad 2 p8 3 /lad 3 p8 4 /lframe# p8 5 /lreset# p8 6 /lclk p8 7 /serirq p4 2 /int 0 cnv ss x in x out v ss reset p4 0 /x cout p4 1 /x cin p1 6 p1 7 /cmp ref p2 6 (led 2 ) p2 5 (led 1 ) p2 4 (led 0 ) p2 3 p2 2 p2 1 p2 0 p3 4 p3 5 p0 0 p0 4 p0 5 p0 6 p0 7 p1 1 p1 2 p1 3 p1 4 p1 5 p1 0 p0 1 p0 2 p3 2 p3 3 p3 6 p3 7 p0 3 p2 7 (led 3 ) p6 0 /an 0 p7 7 /s cl p7 6 /s da p7 5 /int 41 p7 4 /int 31 p7 2 p7 1 p7 0 p5 7 /da 2 /pwm 11 p5 0 /int 5 p4 5 /t x d p7 3 /int 21 p5 5 /cntr 1 p5 4 /cntr 0 p5 6 /da 1 /pwm 01 p4 7 /s rdy /clkrun# p5 2 /int 30 p5 3 /int 40 p5 1 /int 20 p4 6 /s clk 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 m38859ffhp vpp d7 a14 d0 d1 d2 d3 d4 d5 d6 a15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 vss vcc oe ce bsel * we ? :connect to the ceramic oscillation circuit. indicates the flash memory pin. rp ry/by signal cnv ss p4 6 /s clk reset value v pp v ss v ss mode setup method
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 76 software commands table 21 lists the software commands. by entering a software com- mand from the data i/o pins (d 0 d 7 ) in write mode, specify the con- tent of the operation, such as erase or program operation, to be per- formed. the following explains the content of each software command. read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the content of the specified address is output from the data i/o pins (d 0 d 7 ). the read array mode is retained intact until another command is writ- ten. the read array mode is also selected automatically when the device is powered on and after it exits deep power down mode. command read array read status register clear status register program block erase mode write write write write write address x (note 4) x x x x data (d 0 to d 7 ) ff 16 70 16 50 16 40 16 20 16 mode read write write address x wa (note 2) ba (note 3) data (d 0 to d 7 ) srd (note 1) wd (note 2) d0 16 first bus cycle second bus cycle notes 1: srd = status register data 2: wa = write address, wd = write data 3: ba = block address (enter the maximum address of each block) 4: x denotes a given address in the user rom area or boot rom area. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the content of the status register is output from the data i/o pins (d 0 d 7 ) by a read in the second bus cycle. since the content of the status _____ _____ _____ _____ register is updated at the falling edge of oe or ce, the oe or ce signal must be asserted each time the status is read. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr4,sr5 of the status regis- ter after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code 50 16 in the first bus cycle. table 21 software command list (parallel i/o mode) cycle number 1 2 1 2 2
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 77 fig. 75 block erase flowchart program command (40 16 ) the program operation starts when the command code ?0 16 ?is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. whether the write operation is completed can be confirmed by read- _____ ing the status register or the ry/by signal status. when the program starts, the read status register mode is accessed automatically and the content of the status register can be read out from the data bus (d 0 ? 7 ). the status register bit 7 (sr7) is set to ??at the same time the write operation starts and is returned to ??upon completion of the write operation. in this case, the read status register mode re- mains active until the read array command (ff 16 ) is written. ____ the ry/by pin is ??during write operation and ??when the write operation is completed as is the status register bit 7. at program end, program results can be checked by reading the sta- tus register. block erase command (20 16 /d0 16 ) by writing the command code ?0 16 ?in the first bus cycle and the confirmation command code ?0 16 ? in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by signal. at the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to ??at the same time the block erase operation starts and is returned to ??upon comple- tion of the block erase operation. in this case, the read status regis- ter mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by pin is ??during block erase operation and ??when the block erase operation is completed as is the status register bit 7. after the block erase operation is completed, the status register can be read out to know the result of the block erase operation. for de- tails, refer to the section where the status register is detailed. fig. 74 page program flowchart start write 40 16 status register read program completed no yes write address write data sr4=0? program error no yes sr7=1? or ry/by=1? write in this case, the read status register mode remains active until the read array command (ff 16 ) is written. write 20 16 d0 16 block address erase completed no yes start write sr5=0? erase error yes no sr7=1? or ry/by=1? status register read in this case, the read status register mode remains active until the read array command (ff 16 ) is written.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 78 status register the status register indicates status such as whether an erase opera- tion or a program ended successfully or in error. it can be read under the following conditions. (1) in the read array mode when the read status register command (70 16 ) is written and the block address is subsequently read. (2) in the period from when the program write or auto erase starts to when the read array command (ff 16 ) the status register is cleared in the following situations. (1) by writing the clear status register command (50 16 ) (2) in the deep power down mode (3) in the power supply off state table 22 gives the definition of each status register bit. when power is turned on or returning from the deep power down mode, the status register outputs 80 16 . sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. when power is turned on or returning from the deep power down mode, 1 is set for it. this bit is 0 (busy) during the write or erase operations and becomes 1 when these operations ends. erase status (sr5) the erase status reports the operating status of the erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status reports the operating status of the write opera- tion. if a write error occurs, it is set to 1 . when the program status is cleared, it is set to 0 . if 1 is written for any of the sr5, sr4 bits, the program erase all blocks, block erase, commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. also, any commands are not correct, both sr5 and sr4 are set to 1 . full status check results from executed erase and program operations can be known by running a full status check. figure 76 shows a flowchart of the full status check and explains how to remedy errors which occur. ____ ready/busy (ry/by) pin ____ the ry/by pin is an output pin (n-chanel open drain output) which, like the sequencer status (sr7), indicates the operating status of the flash memory. it is l level during auto program or auto erase opera- tions and becomes to the high impedance state (ready state) when ____ these operations end. the ry/by pin requires an external pull-up. table 22 status register each bit of srd0 bits sr7 (d 7 ) sr6 (d 6 ) sr5 (d 5 ) sr4 (d 4 ) sr3 (d 3 ) sr2 (d 2 ) sr1 (d 1 ) sr0 (d 0 ) definition 1 0 sequencer status reserved erase status program status reserved reserved reserved reserved ready - ended in error ended in error - - - - status name busy - ended successfully ended successfully - - - -
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 79 fig. 76 full status check flowchart and remedial procedure for errors read status register sr4=1 and sr5 =1 ? no yes sr5=0? yes block erase error no sr4=0? yes no command sequence error program error end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. note: when one of sr5 to sr4 is set to 1 , none of the program, all blocks erase, or block erase is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 80 cpu reprogram mode in cpu reprogram mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu reprogram mode, only the user rom area shown in figure 72 can be reprogrammed; the boot rom area cannot be repro- grammed. make sure the program and block erase commands are issued for only the user rom area. the control program for cpu reprogram mode can be stored in ei- ther user rom or boot rom area. in the cpu reprogram mode, because the flash memory cannot be read from the cpu, the repro- gram control software must be transferred to internal ram area be- fore it can be executed. microcomputer mode and boot mode the control software for cpu reprogram mode must be programed into the user rom or boot rom area in parallel i/o mode before- hand. (if the control software is programed into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 72 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is released from reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control software in the user rom area. when the microcomputer is released from reset by pulling the p4 6 / s clk pin high, the cnv ss pin high, the cpu starts operating using the control software in the boot rom area (program start address should be stored fffc 16 , fffd 16 ). this mode is called the boot mode . block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. in case of the m38859ff, these are two block. outline performance (cpu reprogram mode) in the cpu reprogram mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. this reprogram control software must be transferred to internal ram be- fore it can be executed. the cpu reprogram mode is accessed by applying 5v 10% to the cnv ss pin and writing 1 for the cpu reprogram mode select bit (bit 1 in address 0ffe 16 ). software commands are accepted once the mode is accessed. use software commands to control software and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 77 shows the flash memory control register. _____ bit 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase opera- tions, it is 0 . otherwise, it is 1 . bit 1 is the cpu reprogram mode select bit. when this bit is set to 1 and 5v 10% are applied to the cnv ss pin, the m38859ff enters the cpu reprogram mode. software commands are accepted once the mode is accessed. in cpu reprogram mode, the cpu becomes unable to access the internal flash memory. therefore, use the con- trol software in ram for write to bit 1. to set this bit to 1 , it is neces- sary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing a 0 . bit 2 is the cpu reprogram mode entry flag. this bit can be read to check whether the cpu reprogram mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. this bit is used when exiting cpu repro- gram mode and when flash memory access has failed. when the cpu reprogram mode select bit is 1 , writing 1 for this bit resets the control circuit. to release the reset, it is necessary to set this bit to 0 . bit 4 is the user area/boot area selection bit. when this bit is set to 1 , boot rom area is accessed, and cpu reprogram mode in boot rom area is available. in boot mode, this bit is set 1 automatically. to set and clear this bit must be operated in ram area. figure 78 shows a flowchart for setting/releasing the cpu repro- gram mode. notes on cpu reprogram mode described below are the precautions to be observed when repro- gram the flash memory in cpu reprogram mode. (1) operation speed during cpu reprogram mode, set the internal clock frequency 4mhz or less using the main clock division ratio selection bits (bit 6,7 at 003b 16 ). (2) instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used during cpu reprogram mode . (3) interrupts inhibited against use the interrupts cannot be used during cpu reprogram mode be- cause they refer to the internal data of the flash memory. (4) watchdog timer in case of the watchdog timer has been running already, the in- ternal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) reset reset is always valid. in case of cnv ss = h when reset is re- leased, boot mode is active. so the program starts from the ad- dress contained in address fffc 16 and fffd 16 in boot rom area.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 81 fig. 77 flash memory control registers fig. 78 cpu rewrite mode set/reset flowchart f l a s h m e m o r y c o n t r o l r e g i s t e r ( a d d r e s s 0 f f e 1 6 ) f m c r ry/by status flag (fmcr0) 0: busy (being programmed or erased) 1: ready cpu reprogram mode select bit (fmcr1) ( note 2 ) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) cpu reprogram mode entry flag (fmcr2) 0: normal mode 1: cpu rewrite mode flash memory reset bit (fmcr3) (note 3 ) 0: normal operation 1: reset user rom area / boot rom area select bit (fmcr4) (note 4 ) 0: user rom area accessed 1: boot rom area accessed reserved bits (indefinite at read/ 0 at write) b0 b7 n o t e s1 : t h e c o n t e n t s o f f l a s h m e m o r y c o n t r o l r e g i s t e r a r e x x x 0 0 0 0 1 j u s t a f t e r r e s e t r e l e a s e . 2 : f o r t h i s b i t t o b e s e t t o 1 , t h e u s e r n e e d s t o w r i t e 0 a n d t h e n 1 t o i t i n s u c c e s s i o n . i f i t i s n o t t h i s p r o c e d u r e , t h i s b i t w i l l n o t b e s e t t o 1 . a d d i t i o n a l l y , i t i s r e q u i r e d t o e n s u r e t h a t n o i n t e r r u p t w i l l b e g e n e r a t e d d u r i n g t h a t i n t e r v a l . u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . 3 : t h i s b i t i s v a l i d w h e n t h e c p u r e w r i t e m o d e s e l e c t b i t i s 1 . s e t t h i s b i t 3 t o 0 s u b s e q u e n t l y a f t e r s e t t i n g b i t 3 t o 1 . 4 : u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . end start execute read array command or reset flash memory by setting flash memory reset bit (by writing 1 and then 0 in succession) (note 2) single-chip mode, or boot mode set cpu mode register (note 1) using software command execute erase, program, or other operation jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu reprogram mode control program to internal ram notes 1: set bit 6,7 (main clock division ratio selection bits ) at cpu mode register (003b 16 ). 2: before exiting the cpu reprogram mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. write 0 to cpu reprogram mode select bit set cpu reprogram mode select bit to 1 (by writing 0 and then 1 in succession)(note 3) check the cpu reprogram mode entry flag *1 *1 program in rom program in ram
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 82 software commands table 23 lists the software commands. after setting the cpu reprogram mode select bit to 1 , write a soft- ware command to specify an erase or program operation. the content of each software command is explained below. read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in next bus cycles, the content of the specified address is read out at the data bus (d 0 d 7 ). the read array mode is retained intact until another command is writ- ten. and after power on and after recover from deep power down mode, this mode is selected also. table 23 list of software commands (cpu rewrite mode) read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr1,sr4 and sr5 of the status register after they have been set. these bits indicate that op- eration has ended in an error. to use this command, write the com- mand code 50 16 in the first bus cycle. command program clear status registe r read array read status registe r x x x x f i r s t b u s c y c l e second bus cycle f f 1 6 70 16 50 16 40 16 w r i t e w r i t e w r i t e w r i t e xs r d r e a d write ( n o t e 1 ) wa (note 2) wd (note 2) block erase x 20 16 write d0 16 w r i t eba (note 3) m o d eaddress mod e address data (d 0 to d 7 ) data (d 0 to d 7 ) ( n o t e 4 ) n o t e 1 : s r d = s t a t u s r e g i s t e r d a t a 2 : w a = w r i t e a d d r e s s , w d = w r i t e d a t a 3 : b a = b l o c k a d d r e s s ( e n t e r t h e m a x i m u m a d d r e s s o f e a c h b l o c k . ) 4 : x d e n o t e s a g i v e n a d d r e s s i n t h e u s e r r o m a r e a . cycle numbe r 1 2 1 2 2
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 83 start write 40 16 status register read program completed no yes program address program data sr4=0? program error no yes sr7=1? or ry/by=1? write fig. 79 program flowchart program command (40 16 ) program operation starts when the command code 40 16 is written in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. whether the program operation is completed can be confirmed by _____ reading the status register or the ry/by status flag. when the pro- gram starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (d0 d7). the status register bit 7 (sr7) is set to 0 at the same time the program operation starts and is returned to 1 upon completion of the program operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. ____ the ry/by status flag is 0 during program operation and 1 when the program operation is completed as is the status register bit 7. at program end, program results can be checked by reading the sta- tus register. block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by status flag. at the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon comple- tion of the block erase operation. in this case, the read status regis- ter mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status register bit 7. after the block erase operation is completed, the status register can be read out to know the result of the block erase operation. for de- tails, refer to the section where the status register is detailed. write 20 16 d0 16 block address erase completed no yes start write sr5=0? erase error yes no sr7=1? or ry/by=1? status register read fig. 80 erase flowchart
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 84 table 24 definition of each bit in status register status register the status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. it can be read in the following ways. (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input table 24 shows the status register. also, the status register can be cleared in the following way. (1) by writing the clear status register command (50 16 ) (2) in the deep power down mode (3) in the power supply off state after a reset, the status register is set to 80 16 . each bit in this register is explained below. sequencer status (sr7) after power-on, and after recover from deep power down mode, the sequencer status is set to 1 (ready). the sequencer status indicates the operating status of the device. this status bit is set to 0 (busy) during program or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of erase operation to the cpu. when an erase error occurs, it is set to 1 . the erase status is reset to 0 when cleared. program status (sr4) the program status informs the operating status of write operation to the cpu. when a write error occurs, it is set to 1 . the program status is reset to 0 when cleared. if 1 is set for any of the sr5 or sr4 bits, the program, erase all blocks, and block erase commands are not accepted. before ex- ecuting these commands, execute the clear status register com- mand (50 16 ) and clear the status register. also, any commands are not correct, both sr5 and sr4 are set to 1 . each bit of srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - status name busy - terminated normally terminated normally - - - -
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 85 full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 81 shows a full sta- tus check flowchart and the action to be taken when each error oc- curs. fig. 81 full status check flowchart and remedial procedure for errors read status register sr4=1 and sr5 =1 ? no yes sr5=0? yes block erase error no sr4=0? yes no command sequence error program error end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. note: when one of sr5 to sr4 is set to 1 , none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 86 functions to inhibit rewriting flash memory to prevent the contents of the flash memory data from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode. rom code protect function the rom code protect function is the function inhibit reading out or modifying the contents of the flash memory version by using the rom code protect control address (ffdb 16 ) during parallel i/o mode. figure 82 shows the rom code protect control address (ffdb 16 ). (this address exists in the user rom area.) if one of the pair of rom code protect bits is set to 0 , rom code protect is turned on, so that the contents of the flash memory data are protected against readout and reprogram. rom code protect is implemented in two levels. if level 2 is selected, the flash memory is protected even against readout by a manufactures inspection test also. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , rom code protect is turned off, so that the contents of the flash memory data can be read out or reprogram. once rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use cpu reprogram mode to re- program the contents of the rom code protect reset bits. fig. 82 rom code protect control address rom code protect control (address ffdb 16 ) ( note 1 ) romcp r e s e r v e d b i t s ( 1 a t r e a d / w r i t e ) r o m c o d e p r o t e c t l e v e l 2 s e t b i t s ( r o m c p 2 ) ( n o t e s 2 , 3 ) b 3 b 2 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d r o m c o d e p r o t e c t r e s e t b i t s ( r o m c r ) ( n o t e 4 ) b 5 b 4 0 0 : p r o t e c t r e m o v e d 0 1 : p r o t e c t s e t b i t s e f f e c t i v e 1 0 : p r o t e c t s e t b i t s e f f e c t i v e 1 1 : p r o t e c t s e t b i t s e f f e c t i v e r o m c o d e p r o t e c t l e v e l 1 s e t b i t s ( r o m c p 1 ) ( n o t e 2 ) b 7 b 6 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d b0 b 7 notes 1 : the contents of rom code protect control register are ff 16 just after reset release. this area is on the rom in the mask rom version. 2 : when rom code protect is turned on, the internal flash memory is protected against readout or modification in parallel i/o mode. 3 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 4 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in standard serial i/o mode or cpu rewrite mode. 1 1
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 87 table 25 flash memory mode electrical characteristics (ta = 25 o c, vcc = 3.3 0.3v unless otherwise noted) flash memory electrical characteristics v pp power source current (read) v pp power source current (program) v pp power source current (erase) ??input voltage (note) ??input voltage (note) v pp power source voltage limits parameter min. typ. max. symbol unit note: input pins for parallel i/o mode. test conditions i pp1 i pp2 i pp3 v il v ih v pp 0 2.0 4.5 100 60 30 0.8 v cc 5.5 a ma ma v v v
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 88 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is ?? af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to ?? then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is ? the instruction with the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to ?? serial i/o continues to output the final bit from the t x d pin after transmission is completed. in clock-synchronous mode, an external clock is used as synchro- nous clock, write transmission data to the transmit buffer register during transfer clock is ?? a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. d-a converter when a d-a converter is not used, set all values of d-ai conver- sion registers (i=1, 2) to ?0 16 ? instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock is twice of the x in period in high- speed mode.
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 89 notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), between power source pin (v cc pin) and analog power source input pin (av ss pin), and between program power source pin (cnvss/v pp ) and gnd pin for flash memory version when on-board reprogramming is executed. besides, connect the capacitor to as close as pos- sible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f?.1 f is recommended. flash memory version the cnv ss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnv ss pin and v ss pin with 1 to 10 k ? resistance. for the mask rom version, there is no operational interference even if cnv ss pin is connected to vss pin via a resistor. electric characteristic differences between mask rom and flash memory version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufac- turing processes. when manufacturing an application system with the flash memory version and then switching to use of the mask rom ver- sion, please perform sufficient evaluations for the commercial samples of the mask rom version. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. for the mask rom confirmation and the mark specifications, refer to the ?itsubishi mcu technical information?homepage: http://www.infomicom.maec.co.jp/indexe.htm
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 90 table 26 absolute maximum ratings power source voltages input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 , v ref reset, x in input voltage p7 0 ?7 7 input voltage cnv ss (note 1) input voltage cnv ss (note 2) output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 , x out output voltage p7 0 ?7 7 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings ?.3 to 4.6 ?.3 to v cc +0.3 ?.3 to 5.8 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 ?.3 to 5.8 500 ?0 to 85 ?0 to 125 v v v v v v v mw ? ? unit t a = 25 ? all voltages are based on v ss . output transistors are cut off. notes 1: flash memory version 2: mask rom version 3.6 v cc v cc v cc v cc 5.5 5.5 5.5 5.5 v cc 0.2v cc 0.8 0.3v cc 0.6 0.16v cc power source voltage power source voltage analog reference voltage analog power source voltage a-d converter input voltage an 0 ?n 7 ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 , reset, cnv ss ??input voltage p7 0 ?7 7 ??input voltage (when ttl input level is selected) p7 0 ?7 5 ??input voltage (when i 2 c-bus input level is selected) s da , s cl ??input voltage (when smbus input level is selected) s da , s cl ??input voltage x in , x cin ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7, p8 0 ?8 7, reset, cnv ss ??input voltage (when ttl input level is selected) p7 0 ?7 5 ??input voltage (when i 2 c-bus input level is selected) s da , s cl ??input voltage (when smbus input level is selected) s da , s cl ??input voltage x in , x cin v cc v ss v ref av ss v ia v ih v ih v ih v ih v ih v ih v il v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v v v v unit table 27 recommended operating conditions (v cc = 3.3 v ?0.3v, t a = ?0 to 85 ?, unless otherwise noted) 3.0 2.0 2.7 av ss 0.8v cc 0.8v cc 2.0 0.7v cc 1.4 0.8v cc 0 0 0 0 0 3.3 0 0 typ. max. when a-d converter is used when d-a converter is used electrical characteristics
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 91 table 28 recommended operating conditions (v cc = 3.3 v ?0.3v, t a = ?0 to 85 ?, unless otherwise noted) ?0 ?0 80 80 80 ?0 ?0 40 40 40 ??total peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p8 0 ?8 7 ??total peak output current p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 ??total peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p8 0 ?8 7 ??total peak output current p2 4 ?2 7 ??total peak output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 ??total average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p8 0 ?8 7 ??total average output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 ??total average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p8 0 ?8 7 ??total average output current p2 4 ?2 7 ??total average output current p4 0 ?4 7 ,p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma unit typ. max. note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. table 29 recommended operating conditions (v cc = 3.3 v ?0.3v, t a = ?0 to 85 ?, unless otherwise noted) ?0 10 20 ? 5 15 8 50 ??peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 (note 1) ??peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 (note 1) ??peak output current p2 4 ?2 7 (note 1) ??average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p8 0 ?8 7 (note 2) ??average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 3 , p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 (note 2) ??peak output current p2 4 ?2 7 (note 2) main clock input oscillation frequency (note 3) sub-clock input oscillation frequency (notes 3, 4) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x cin ) symbol parameter limits min. ma ma ma ma ma ma mhz khz unit typ. max. notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50%. 4: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 32.768
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 92 table 30 electrical characteristics (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) ??output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p8 0 ?8 7 (note) ??output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 hysteresis cntr 0 , cntr 1 , int 0 , int 1 int 20 ?nt 40 , int 21 ?nt 41 , int 5 p3 0 ?3 7 , rxd, s clk , lreset lframe, lclk, serirq ??input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 p3 0 ?3 7 , p4 0 ?4 7 , p5 0 ?5 7 p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 reset,cnv ss ??input current x in ??input current p3 0 ?3 7 (at pull-up) ram hold voltage limits v v v v a a a a a v parameter min. typ. max. symbol unit note: p0 0 ?0 3 are measured when the p0 0 ?0 3 output structure selection bit (bit 0 of pctl1) is ?? p0 4 ?0 7 are measured when the p0 4 ?0 7 output structure selection bit (bit 1 of pctl1) is ?? p1 0 ?1 3 are measured when the p1 0 ?1 3 output structure selection bit (bit 2 of pctl1) is ?? p1 4 ?1 7 are measured when the p1 4 ?1 7 output structure selection bit (bit 3 of pctl1) is ?? p4 2 , p4 3 , p4 4 , and p4 6 are measured when the p4 output structure selection bit (bit 2 of pctl2) is ?? p4 5 is measured when the p4 5 /t x d p-channel output disable bit (bit 4 of uartcon) is ?? i oh = ? ma i ol = 5 ma i ol = 1.6 ma v i = v cc (pin floating. pull-up transistors ?ff? v i = v cc v i = v ss (pin floating. pull-up transistors ?ff? v i = v ss v i = v ss when clock stopped v cc ?.0 ?3 2.0 test conditions 0.4 3 ? ?0 1.0 0.4 5.0 ?.0 ?00 3.6 v oh v ol v t+ ? t i ih i ih i il i il i il v ram
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 93 table 31 electrical characteristics (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, mask rom version unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors ?ff high-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors ?ff middle-speed mode f(x in ) = 8 mhz f(x cin ) = stopped output transistors ?ff middle-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = stopped output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff additional current when a-d converter works f(x in ) = 8 mhz additional current when lpc i/f functions lclk = 33 mhz all oscillation stopped (in stp state) output transistors ?ff test conditions 7 2 4 1.5 40 20 1.0 10 i cc ta = 25 ? ta = 85 ? 2.5 0.8 1.5 0.6 15 10 500 1.5 0.1 ma ma ma ma a a a ma a a
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 94 table 32 electrical characteristics (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, flash memory version, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors ?ff high-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors ?ff middle-speed mode f(x in ) = 8 mhz f(x cin ) = stopped output transistors ?ff middle-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = stopped output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?ff low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?ff additional current when a-d converter works f(x in ) = 8 mhz additional current when lpc i/f functions lclk = 33 mhz all oscillation stopped (in stp state) output transistors ?ff test conditions i cc ta = 25 ? ta = 85 ? 6.0 0.8 2.0 0.6 100 10 500 1.5 0.1 ma ma ma ma a a a ma a a 13 2 7 1.5 200 20 1.0 10
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 95 table 33 a-d converter characteristics (1) (v cc = 3.3 v ?0.3v, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) 10-bit a-d mode (when conversion mode selection bit (bit 7 of ad2) is ?? bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 10 ? 61 100 200 5 5.0 v cc = v ref = 3.3 v v ref = 3.3 v v ref = 3.3 v unit limits parameter t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped symbol table 36 comparator characteristics (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) table 34 a-d converter characteristics (2) (v cc = 3.3 v ?0.3v, v ref = 2.0 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) 8-bit a-d mode (when conversion mode selection bit (bit 7 of ad2) is ?? table 35 d-a converter characteristics (v cc = 3.3 v ?0.3v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) bit lsb 2tc(x in ) k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 12 50 typ. 35 150 max. 8 ? 50 100 200 5 5.0 v cc = v ref = 3.3 v v ref = 3.3 v v ref = 3.3 v unit limits parameter t conv r ladder i vref i i(ad) test conditions at a-d converter operated at a-d converter stopped symbol bits % s k ? ma resolution absolute accuracy setting time output resistor reference power source input current min. 2 typ. 3.5 max. 8 1.0 3 5 2.1 unit limits parameter tsu ro i vref test conditions symbol lsb s s v a k ? v v absolute accuracy conversion time analog input voltage analog input current ladder resistor internal reference voltage external reference input voltage min. 0 20 v cc /32 typ. 40 29v cc /32 max. 1/2 3.5 7 v cc 5.0 50 v cc unit limits parameter t conv v ia i ia r ladder cmp ref test conditions symbol 1lsb = v cc /16 at 8 mhz operating at 4 mhz operating
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 96 table 37 timing requirements (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) reset input ??pulse width main clock input cycle time main clock input ??pulse width main clock input ??pulse width sub-clock input cycle time sub-clock input ??pulse width sub-clock input ??pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ??pulse width cntr 0 , cntr 1 input ??pulse width t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) limits tc (xin) ns ns ns s s s ns ns ns ns ns parameter min. 16 125 50 50 20 5 5 200 80 80 80 80 typ. max. symbol unit note : when bit 6 of siocon is ??(clock synchronous). divide this value by four when bit 6 of siocon is ??(uart). t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) serial i/o clock input cycle time (note) serial i/o clock input ??pulse width (note) serial i/o clock input ??pulse width (note) serial i/o input setup time serial i/o input hold time int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width int 0 , int 1, int 20, int 30, int 40 , int 21, int 31, int 41 input ??pulse width 800 370 370 220 100 ns ns ns ns ns table 38 switching characteristics (v cc = 3.3 v ?0.3v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) serial i/o clock output ??pulse width serial i/o clock output ??pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) t wh (s clk ) t wl (s clk ) t d (s clk -t x d) t v (s clk -t x d) t r (s clk ) t f (s clk ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns parameter min. t c (s clk )/2?0 t c (s clk )/2?0 ?0 typ. 10 10 max. 140 30 30 30 30 symbol unit notes 1: when the p4 5 /t x d p-channel output disable bit (bit 4 of uartcon) is ?? 2: the x out pin is excluded. test conditions fig. 90
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 97 fig. 83 circuit for measuring output switching characteristics measurement output pin 50pf cmos out p ut
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 98 fig. 84 timing diagram 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in) t c(x in ) x in 0.2v cc 0.8v cc t w(reset) reset t f t r 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) t c(cntr) t d(s clk -t x d) t v(s clk -t x d) t c(s clk ) t wl(s clk ) t wh(s clk ) t h(s clk- r x d) t su(r x d - s clk ) t x d r x d s clk int 0, int 1, int 5 int 20, int 30, int 40 int 21, int 31, int 41 cntr 0 , cntr 1 timing diagram 0.2v cc t wl(x cin ) 0.8v cc t wh(x cin) t c(x cin ) x cin
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 99 symbol parameter unit table 39 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition hold time for s cl clock = 0 rising time of both s cl and s da signals data hold time hold time for s cl clock = 1 falling time of both s cl and s da signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. s s s ns s s ns ns s s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line fig. 85 timing diagram of multi-master i 2 c-bus 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 300 0.9 300 t b u f t h d : s t a t h d : d a t t l o w t r t f t h i g h t s u : d a t t s u : s t a t hd:sta t s u : s t o s c l p s s r p s d a s: s t a r t c o n d i t i o n s r: r e s t a r t c o n d i t i o n p: s t o p c o n d i t i o n
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 100 table 40 timing requirements and switching characteristics (v cc = 3.3 v 0.3v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) fig. 86 timing diagram of lpc interface and serialized irq standard parameter min. 30 11 11 13 7 0 2 2 symbol unit lclk clock input cycle time lclk clock input h pulse width lclk clock input l pulse width input set up time lad 3 to lad 0 , serirq, clkrun, lframe input hold time lad 3 to lad 0 , clkrun, lframe serirq, lad 3 to lad 0 , serirq, clkrun valid delay time lad 3 to lad 0 ,serirq,clkrun floating output delay time t c(clk) t wh(clk) t wl(clk) t su(d-c) t h(c-d) t v(c-d) t off(a-f) typ. ns ns ns ns ns ns ns t wh (clk) t wl (clk) t c (clk) tsu(d-c) th(c-d) tv(c-d) vih vil toff(a-f) lclk lad[3:0] serirq, clkrun, lframe (input) lad[3:0] serirq, clkrun (active output) lad[3:0] serirq, clkrun (floating output ) timing diagrams of lpc bus interface and serial interrupt output max. 15 28
3885 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers ? 2002 mitsubishi electric corp. new publication, effective june 2002. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan package outline lqfp80-p-1212-0.5 weight(g) 0.47 jedec code eiaj package code lead material cu alloy 80p6q-a plastic 80pin 12 ? 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 12.4 m e 12.4 10 0 0.1 1.0 0.7 0.5 0.3 14.2 14.0 13.8 14.2 14.0 13.8 0.5 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e a f e h d e h e d 1 20 21 40 41 60 61 80 y lp 0.45 0.6 0.25 0.75 0.08 x a3 m d l 2 b 2 m e e recommended mount pad b x m a 1 a 2 l 1 l detail f lp a3 c mmp
revision history 3885 group data sheet rev. date description page summary (1/x) 1.0 06/04/02 first edition issued.

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